rocketchip: remove obsolete pDevices used during TL1=>2 migration
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@ -27,7 +27,6 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
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// the following variables will be refactored properly with TL2
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// the following variables will be refactored properly with TL2
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val pInterrupts = new RangeManager
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val pInterrupts = new RangeManager
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val pBusMasters = new RangeManager
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val pBusMasters = new RangeManager
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val pDevices = new ResourceManager[AddrMapEntry]
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TLImp.emitMonitors = q(TLEmitMonitors)
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TLImp.emitMonitors = q(TLEmitMonitors)
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@ -44,10 +43,10 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
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hasSupervisor = q(UseVM)
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hasSupervisor = q(UseVM)
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)
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)
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lazy val genGlobalAddrMap = GenerateGlobalAddrMap(q, pDevices.get, peripheryManagers)
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lazy val genGlobalAddrMap = GenerateGlobalAddrMap(q, peripheryManagers)
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private val qWithMap = q.alterPartial({case GlobalAddrMap => genGlobalAddrMap})
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private val qWithMap = q.alterPartial({case GlobalAddrMap => genGlobalAddrMap})
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lazy val genConfigString = GenerateConfigString(qWithMap, c, pDevices.get, peripheryManagers)
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lazy val genConfigString = GenerateConfigString(qWithMap, c, peripheryManagers)
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implicit val p = qWithMap.alterPartial({
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implicit val p = qWithMap.alterPartial({
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case ConfigString => genConfigString
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case ConfigString => genConfigString
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case NCoreplexExtClients => pBusMasters.sum})
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case NCoreplexExtClients => pBusMasters.sum})
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@ -53,7 +53,7 @@ class GlobalVariable[T] {
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}
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}
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object GenerateGlobalAddrMap {
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object GenerateGlobalAddrMap {
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def apply(p: Parameters, pDevicesEntries: Seq[AddrMapEntry], peripheryManagers: Seq[TLManagerParameters]) = {
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def apply(p: Parameters, peripheryManagers: Seq[TLManagerParameters]) = {
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lazy val cBusIOAddrMap: AddrMap = {
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lazy val cBusIOAddrMap: AddrMap = {
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val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
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val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
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entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
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entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
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@ -90,7 +90,7 @@ object GenerateGlobalAddrMap {
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}).flatten.toList
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}).flatten.toList
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lazy val tl2AddrMap = new AddrMap(uniquelyNamedTL2Devices, collapse = true)
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lazy val tl2AddrMap = new AddrMap(uniquelyNamedTL2Devices, collapse = true)
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lazy val pBusIOAddrMap = new AddrMap(AddrMapEntry("TL2", tl2AddrMap) +: (p(ExtMMIOPorts) ++ pDevicesEntries), collapse = true)
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lazy val pBusIOAddrMap = new AddrMap(AddrMapEntry("TL2", tl2AddrMap) +: p(ExtMMIOPorts), collapse = true)
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val memBase = 0x80000000L
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val memBase = 0x80000000L
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val memSize = p(ExtMemSize)
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val memSize = p(ExtMemSize)
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@ -105,7 +105,7 @@ object GenerateGlobalAddrMap {
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}
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}
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object GenerateConfigString {
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object GenerateConfigString {
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def apply(p: Parameters, c: CoreplexConfig, pDevicesEntries: Seq[AddrMapEntry], peripheryManagers: Seq[TLManagerParameters]) = {
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def apply(p: Parameters, c: CoreplexConfig, peripheryManagers: Seq[TLManagerParameters]) = {
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val addrMap = p(GlobalAddrMap)
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val addrMap = p(GlobalAddrMap)
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val plicAddr = addrMap("io:cbus:plic").start
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val plicAddr = addrMap("io:cbus:plic").start
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val clint = CoreplexLocalInterrupterConfig(0, addrMap("io:pbus:TL2:clint").start)
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val clint = CoreplexLocalInterrupterConfig(0, addrMap("io:pbus:TL2:clint").start)
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@ -160,13 +160,6 @@ object GenerateConfigString {
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res append " };\n"
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res append " };\n"
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}
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}
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res append "};\n"
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res append "};\n"
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pDevicesEntries foreach { entry =>
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val region = addrMap("io:pbus:" + entry.name)
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res append s"${entry.name} {\n"
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res append s" addr 0x${region.start.toString(16)};\n"
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res append s" size 0x${region.size.toString(16)}; \n"
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res append "}\n"
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}
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peripheryManagers.foreach { manager => res append manager.dts }
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peripheryManagers.foreach { manager => res append manager.dts }
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res append '\u0000'
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res append '\u0000'
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res.toString
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res.toString
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