tilelink: PMP controlled BusBlocker prevents bus accesses
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108
src/main/scala/devices/tilelink/BusBlocker.scala
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108
src/main/scala/devices/tilelink/BusBlocker.scala
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.devices.tilelink
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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case class BusBlockerParams(
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controlAddress: BigInt,
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controlBeatBytes: Int,
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deviceBeatBytes: Int,
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pmpRegisters: Int)
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{
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val page = 4096
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val size = (((pmpRegisters * 8) + page - 1) / page) * page
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require (pmpRegisters > 0)
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require (controlAddress > 0)
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require (controlAddress % size == 0)
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require (controlBeatBytes > 0 && isPow2(controlBeatBytes))
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require (deviceBeatBytes > 0 && isPow2(deviceBeatBytes))
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}
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case class DevicePMPParams(addressBits: Int)
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class DevicePMP(params: DevicePMPParams) extends GenericParameterizedBundle(params)
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{
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require (params.addressBits > 12)
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val l = UInt(width = 1) // locked
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val a = UInt(width = 1) // LSB of A (0=disabled, 1=TOR)
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val r = UInt(width = 1)
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val w = UInt(width = 1)
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val addr_hi = UInt(width = params.addressBits-12)
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def address = Cat(addr_hi, UInt(0, width=12))
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def fields(locked: Bool): Seq[RegField] = {
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def field(bits: Int, reg: UInt) =
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RegField(bits, RegReadFn(reg), RegWriteFn((wen, data) => {
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when (wen && !locked) { reg := data }
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Bool(true)
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}))
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Seq(
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RegField(10),
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field(params.addressBits-12, addr_hi),
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RegField(56 - (params.addressBits-2)),
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field(1, r),
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field(1, w),
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RegField(1), // x
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field(1, a),
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RegField(3), // a high + 2 reserved
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field(1, l))
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}
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}
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object DevicePMP
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{
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def apply(addressBits: Int) = {
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val out = Wire(new DevicePMP(DevicePMPParams(addressBits)))
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out.l := UInt(0)
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out.a := UInt(1) // TOR
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out.r := UInt(0)
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out.w := UInt(0)
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out.addr_hi := ~UInt(0, width=addressBits-12)
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out
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}
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}
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class BusBlocker(params: BusBlockerParams)(implicit p: Parameters) extends TLBusBypassBase(params.deviceBeatBytes)
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{
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val device = new SimpleDevice("bus-blocker", Seq("sifive,bus-blocker0"))
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val controlNode = TLRegisterNode(
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address = Seq(AddressSet(params.controlAddress, params.size-1)),
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device = device,
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beatBytes = params.controlBeatBytes)
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val ctl = controlNode.bundleIn
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val in = nodeIn.bundleIn
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val out = nodeOut.bundleOut
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}
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// We need to be able to represent +1 larger than the largest populated address
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val addressBits = log2Ceil(nodeOut.edgesOut(0).manager.maxAddress+1+1)
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val pmps = RegInit(Vec.fill(params.pmpRegisters) { DevicePMP(addressBits) })
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val locks = (pmps.map(_.l) zip (UInt(0) +: pmps.map(_.l))) map { case (x, n) => x | n }
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controlNode.regmap(0 -> (pmps zip locks).map { case (p, l) => p.fields(l(0)) }.toList.flatten)
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val in = io.in(0)
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val edge = nodeIn.edgesIn(0)
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// Determine if a request is allowed
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val needW = in.a.bits.opcode =/= TLMessages.Get
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val needR = in.a.bits.opcode =/= TLMessages.PutFullData && in.a.bits.opcode =/= TLMessages.PutPartialData
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val lte = Bool(false) +: pmps.map(in.a.bits.address < _.address)
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val sel = (pmps.map(_.a) zip (lte.init zip lte.tail)) map { case (a, (l, r)) => a(0) && !l && r }
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val ok = pmps.map(p => (p.r(0) || !needR) && (p.w(0) || !needW))
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val allow = PriorityMux(sel :+ Bool(true), ok :+ Bool(true)) // no match => allow
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bar.module.io.bypass := !allow
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}
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}
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@ -10,19 +10,23 @@ import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import scala.math.min
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class TLBusBypass(beatBytes: Int)(implicit p: Parameters) extends LazyModule
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abstract class TLBusBypassBase(beatBytes: Int)(implicit p: Parameters) extends LazyModule
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{
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private val nodeIn = TLInputNode()
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private val nodeOut = TLOutputNode()
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protected val nodeIn = TLInputNode()
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protected val nodeOut = TLOutputNode()
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val node = NodeHandle(nodeIn, nodeOut)
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private val bar = LazyModule(new TLBusBypassBar)
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private val everything = Seq(AddressSet(0, BigInt("ffffffffffffffffffffffffffffffff", 16))) // 128-bit
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private val error = LazyModule(new TLError(ErrorParams(everything), beatBytes))
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protected val bar = LazyModule(new TLBusBypassBar)
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protected val everything = Seq(AddressSet(0, BigInt("ffffffffffffffffffffffffffffffff", 16))) // 128-bit
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protected val error = LazyModule(new TLError(ErrorParams(everything), beatBytes))
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bar.node := nodeIn
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error.node := bar.node
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nodeOut := bar.node
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}
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class TLBusBypass(beatBytes: Int)(implicit p: Parameters) extends TLBusBypassBase(beatBytes)
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{
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = nodeIn.bundleIn
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@ -33,7 +37,7 @@ class TLBusBypass(beatBytes: Int)(implicit p: Parameters) extends LazyModule
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}
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}
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private class TLBusBypassBar(implicit p: Parameters) extends LazyModule
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class TLBusBypassBar(implicit p: Parameters) extends LazyModule
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{
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// The client only sees the second slave port
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val node = TLNexusNode(
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