riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

add multichannel NASTI support in Verilog testbench

Browse Source
This commit is contained in:
Yunsup Lee
2015-10-30 21:14:33 -07:00
committed by Howard Mao
parent 9dabcab9c2
commit 0d245741bc
10 changed files with 446 additions and 376 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
vsim/Makefrag-verilog
View File

@ -13,6 +13,7 @@ $(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).v
echo "\`ifndef CONST_VH" > $@
echo "\`define CONST_VH" >> $@
sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $(patsubst %.v,%.prm,$<) >> $@
echo "\`define TBVFRAG \"$(MODEL).$(CONFIG).tb.vfrag\"" >> $@
echo "\`endif // CONST_VH" >> $@
$(generated_dir)/memdessertMemDessert.$(CONFIG).v $(generated_dir)/memdessertMemDessert.$(CONFIG).d: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala