diff --git a/csrc/emulator.cc b/csrc/emulator.cc
index 3eb38547..c1671831 100644
--- a/csrc/emulator.cc
+++ b/csrc/emulator.cc
@@ -69,7 +69,7 @@ int main(int argc, char** argv)
   srand(random_seed);
   tile.init(random_seed);
 
-  uint64_t mem_width = tile.Top__io_mem_r_bits_data.width() / 8;
+  uint64_t mem_width = tile.Top__io_mem_0_r_bits_data.width() / 8;
 
   // Instantiate and initialize main memory
   mm_t* mm = dramsim2 ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t);
@@ -106,19 +106,19 @@ int main(int argc, char** argv)
 
   while (!htif->done() && trace_count < max_cycles && ret == 0)
   {
-    tile.Top__io_mem_ar_ready = LIT<1>(mm->ar_ready());
-    tile.Top__io_mem_aw_ready = LIT<1>(mm->aw_ready());
-    tile.Top__io_mem_w_ready = LIT<1>(mm->w_ready());
+    tile.Top__io_mem_0_ar_ready = LIT<1>(mm->ar_ready());
+    tile.Top__io_mem_0_aw_ready = LIT<1>(mm->aw_ready());
+    tile.Top__io_mem_0_w_ready = LIT<1>(mm->w_ready());
 
-    tile.Top__io_mem_b_valid = LIT<1>(mm->b_valid());
-    tile.Top__io_mem_b_bits_resp = LIT<64>(mm->b_resp());
-    tile.Top__io_mem_b_bits_id = LIT<64>(mm->b_id());
+    tile.Top__io_mem_0_b_valid = LIT<1>(mm->b_valid());
+    tile.Top__io_mem_0_b_bits_resp = LIT<64>(mm->b_resp());
+    tile.Top__io_mem_0_b_bits_id = LIT<64>(mm->b_id());
 
-    tile.Top__io_mem_r_valid = LIT<1>(mm->r_valid());
-    tile.Top__io_mem_r_bits_resp = LIT<64>(mm->r_resp());
-    tile.Top__io_mem_r_bits_id = LIT<64>(mm->r_id());
-    tile.Top__io_mem_r_bits_last = LIT<1>(mm->r_last());
-    memcpy(tile.Top__io_mem_r_bits_data.values, mm->r_data(), mem_width);
+    tile.Top__io_mem_0_r_valid = LIT<1>(mm->r_valid());
+    tile.Top__io_mem_0_r_bits_resp = LIT<64>(mm->r_resp());
+    tile.Top__io_mem_0_r_bits_id = LIT<64>(mm->r_id());
+    tile.Top__io_mem_0_r_bits_last = LIT<1>(mm->r_last());
+    memcpy(tile.Top__io_mem_0_r_bits_data.values, mm->r_data(), mem_width);
 
     try {
       tile.clock_lo(LIT<1>(0));
@@ -129,25 +129,25 @@ int main(int argc, char** argv)
     }
 
     mm->tick(
-      tile.Top__io_mem_ar_valid.lo_word(),
-      tile.Top__io_mem_ar_bits_addr.lo_word(),
-      tile.Top__io_mem_ar_bits_id.lo_word(),
-      tile.Top__io_mem_ar_bits_size.lo_word(),
-      tile.Top__io_mem_ar_bits_len.lo_word(),
+      tile.Top__io_mem_0_ar_valid.lo_word(),
+      tile.Top__io_mem_0_ar_bits_addr.lo_word(),
+      tile.Top__io_mem_0_ar_bits_id.lo_word(),
+      tile.Top__io_mem_0_ar_bits_size.lo_word(),
+      tile.Top__io_mem_0_ar_bits_len.lo_word(),
 
-      tile.Top__io_mem_aw_valid.lo_word(),
-      tile.Top__io_mem_aw_bits_addr.lo_word(),
-      tile.Top__io_mem_aw_bits_id.lo_word(),
-      tile.Top__io_mem_aw_bits_size.lo_word(),
-      tile.Top__io_mem_aw_bits_len.lo_word(),
+      tile.Top__io_mem_0_aw_valid.lo_word(),
+      tile.Top__io_mem_0_aw_bits_addr.lo_word(),
+      tile.Top__io_mem_0_aw_bits_id.lo_word(),
+      tile.Top__io_mem_0_aw_bits_size.lo_word(),
+      tile.Top__io_mem_0_aw_bits_len.lo_word(),
 
-      tile.Top__io_mem_w_valid.lo_word(),
-      tile.Top__io_mem_w_bits_strb.lo_word(),
-      tile.Top__io_mem_w_bits_data.values,
-      tile.Top__io_mem_w_bits_last.lo_word(),
+      tile.Top__io_mem_0_w_valid.lo_word(),
+      tile.Top__io_mem_0_w_bits_strb.lo_word(),
+      tile.Top__io_mem_0_w_bits_data.values,
+      tile.Top__io_mem_0_w_bits_last.lo_word(),
 
-      tile.Top__io_mem_r_ready.to_bool(),
-      tile.Top__io_mem_b_ready.to_bool()
+      tile.Top__io_mem_0_r_ready.to_bool(),
+      tile.Top__io_mem_0_b_ready.to_bool()
     );
 
     if (tile.Top__io_host_clk_edge.to_bool())
diff --git a/csrc/vcs_main.cc b/csrc/vcs_main.cc
index 8b0a3e31..32fdd1b9 100644
--- a/csrc/vcs_main.cc
+++ b/csrc/vcs_main.cc
@@ -16,8 +16,10 @@ extern int vcs_main(int argc, char** argv);
 
 static htif_emulator_t* htif;
 static unsigned htif_bytes;
-static mm_t* mm;
+static unsigned mem_channels;
+static mm_t** mm;
 static const char* loadmem;
+static bool dramsim = false;
 
 void htif_fini(vc_handle failure)
 {
@@ -28,7 +30,6 @@ void htif_fini(vc_handle failure)
 
 int main(int argc, char** argv)
 {
-  bool dramsim = false;
   unsigned long memsz_mb = MEM_SIZE / (1024*1024);
 
   for (int i = 1; i < argc; i++)
@@ -39,7 +40,6 @@ int main(int argc, char** argv)
       loadmem = argv[i]+9;
   }
 
-  mm = dramsim ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t);
   htif = new htif_emulator_t(memsz_mb,
           std::vector<std::string>(argv + 1, argv + argc));
 
@@ -48,6 +48,8 @@ int main(int argc, char** argv)
 }
 
 void memory_tick(
+  vc_handle channel,
+
   vc_handle ar_valid,
   vc_handle ar_ready,
   vc_handle ar_addr,
@@ -80,43 +82,15 @@ void memory_tick(
   vc_handle b_resp,
   vc_handle b_id)
 {
-  uint32_t write_data[mm->get_word_size()/sizeof(uint32_t)];
-  for (size_t i = 0; i < mm->get_word_size()/sizeof(uint32_t); i++)
+  int c = vc_4stVectorRef(channel)->d;
+  assert(c < mem_channels);
+  mm_t* mmc = mm[c];
+
+  uint32_t write_data[mmc->get_word_size()/sizeof(uint32_t)];
+  for (size_t i = 0; i < mmc->get_word_size()/sizeof(uint32_t); i++)
     write_data[i] = vc_4stVectorRef(w_data)[i].d;
 
-  vc_putScalar(ar_ready, mm->ar_ready());
-  vc_putScalar(aw_ready, mm->aw_ready());
-  vc_putScalar(w_ready, mm->w_ready());
-  vc_putScalar(b_valid, mm->b_valid());
-  vc_putScalar(r_valid, mm->r_valid());
-  vc_putScalar(r_last, mm->r_last());
-
-  vec32 d[mm->get_word_size()/sizeof(uint32_t)];
-
-  d[0].c = 0;
-  d[0].d = mm->b_resp();
-  vc_put4stVector(b_resp, d);
-
-  d[0].c = 0;
-  d[0].d = mm->b_id();
-  vc_put4stVector(b_id, d);
-
-  d[0].c = 0;
-  d[0].d = mm->r_resp();
-  vc_put4stVector(r_resp, d);
-
-  d[0].c = 0;
-  d[0].d = mm->r_id();
-  vc_put4stVector(r_id, d);
-
-  for (size_t i = 0; i < mm->get_word_size()/sizeof(uint32_t); i++)
-  {
-    d[i].c = 0;
-    d[i].d = ((uint32_t*)mm->r_data())[i];
-  }
-  vc_put4stVector(r_data, d);
-
-  mm->tick
+  mmc->tick
   (
     vc_getScalar(ar_valid),
     vc_4stVectorRef(ar_addr)->d,
@@ -138,16 +112,58 @@ void memory_tick(
     vc_getScalar(r_ready),
     vc_getScalar(b_ready)
   );
+
+  vc_putScalar(ar_ready, mmc->ar_ready());
+  vc_putScalar(aw_ready, mmc->aw_ready());
+  vc_putScalar(w_ready, mmc->w_ready());
+  vc_putScalar(b_valid, mmc->b_valid());
+  vc_putScalar(r_valid, mmc->r_valid());
+  vc_putScalar(r_last, mmc->r_last());
+
+  vec32 d[mmc->get_word_size()/sizeof(uint32_t)];
+
+  d[0].c = 0;
+  d[0].d = mmc->b_resp();
+  vc_put4stVector(b_resp, d);
+
+  d[0].c = 0;
+  d[0].d = mmc->b_id();
+  vc_put4stVector(b_id, d);
+
+  d[0].c = 0;
+  d[0].d = mmc->r_resp();
+  vc_put4stVector(r_resp, d);
+
+  d[0].c = 0;
+  d[0].d = mmc->r_id();
+  vc_put4stVector(r_id, d);
+
+  for (size_t i = 0; i < mmc->get_word_size()/sizeof(uint32_t); i++)
+  {
+    d[i].c = 0;
+    d[i].d = ((uint32_t*)mmc->r_data())[i];
+  }
+  vc_put4stVector(r_data, d);
 }
 
-void htif_init(vc_handle htif_width, vc_handle mem_width)
+void htif_init(
+  vc_handle n_mem_channel,
+  vc_handle htif_width, vc_handle mem_width)
 {
+  mem_channels = vc_4stVectorRef(n_mem_channel)->d;
+
   int mw = vc_4stVectorRef(mem_width)->d;
   assert(mw && (mw & (mw-1)) == 0);
-  mm->init(MEM_SIZE, mw/8, LINE_SIZE);
 
-  if (loadmem)
-    load_mem(mm->get_data(), loadmem);
+  mm = new mm_t*[mem_channels];
+
+  for (int i=0; i<mem_channels; i++) {
+    mm[i] = dramsim ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t);
+    mm[i]->init(MEM_SIZE, mw/8, LINE_SIZE);
+
+    if (loadmem)
+      load_mem(mm[i]->get_data(), loadmem);
+  }
 
   vec32* w = vc_4stVectorRef(htif_width);
   assert(w->d <= 32 && w->d % 8 == 0); // htif_tick assumes data fits in a vec32
diff --git a/fsim/Makefrag b/fsim/Makefrag
index 6a9dab4e..bcbdb667 100644
--- a/fsim/Makefrag
+++ b/fsim/Makefrag
@@ -43,6 +43,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	-e vcs_main \
 	$(RISCV)/lib/libfesvr.so \
 	$(sim_dir)/libdramsim.a \
+	+incdir+$(generated_dir) \
 	+define+FPGA \
 	+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
 	+define+PRINTF_COND=$(TB).verbose \
diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index 9295560f..e577f79f 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -154,11 +154,11 @@ class DefaultConfig extends Config (
           dataBits = site(CacheBlockBytes)*8)
       case TLKey("Outermost") => site(TLKey("L2toMC")).copy(dataBeats = site(MIFDataBeats))
       case NTiles => Knob("NTILES")
-      case NMemoryChannels => 1
+      case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
       case NBanksPerMemoryChannel => Knob("NBANKS")
       case NOutstandingMemReqsPerChannel => site(NBanksPerMemoryChannel)*(site(NAcquireTransactors)+2)
       case BankIdLSB => 0
-      case CacheBlockBytes => 64
+      case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
       case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
       case UseBackupMemoryPort => true
       case MMIOBase => BigInt(1 << 30) // 1 GB
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 7717f8da..884cffad 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -68,12 +68,7 @@ class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
 }
 
 class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
-  val mem = new NastiIO
-}
-
-class MultiChannelTopIO(implicit p: Parameters) extends BasicTopIO()(p) {
   val mem = Vec(new NastiIO, nMemChannels)
-  val mmio = new NastiIO
 }
 
 object TopUtils {
@@ -94,29 +89,6 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
   implicit val p = topParams
   val io = new TopIO
 
-  val temp = Module(new MultiChannelTop)
-  val arb = Module(new NastiArbiter(nMemChannels))
-  arb.io.master <> temp.io.mem
-  io.mem.ar <> Queue(arb.io.slave.ar)
-  io.mem.aw <> Queue(arb.io.slave.aw)
-  io.mem.w  <> Queue(arb.io.slave.w)
-  arb.io.slave.r <> Queue(io.mem.r)
-  arb.io.slave.b <> Queue(io.mem.b)
-  io.mem_backup_ctrl <> temp.io.mem_backup_ctrl
-  io.host <> temp.io.host
-
-  // Memory cache type should be normal non-cacheable bufferable
-  io.mem.ar.bits.cache := UInt("b0011")
-  io.mem.aw.bits.cache := UInt("b0011")
-
-  // tie off the mmio port
-  val errslave = Module(new NastiErrorSlave)
-  errslave.io <> temp.io.mmio
-}
-
-class MultiChannelTop(implicit val p: Parameters) extends Module with HasTopLevelParameters {
-  val io = new MultiChannelTopIO
-
   // Build an Uncore and a set of Tiles
   val innerTLParams = p.alterPartial({case TLId => "L1toL2" })
   val uncore = Module(new Uncore()(innerTLParams))
@@ -139,8 +111,15 @@ class MultiChannelTop(implicit val p: Parameters) extends Module with HasTopLeve
   uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten
   io.host <> uncore.io.host
   io.mem <> uncore.io.mem
-  io.mmio <> uncore.io.mmio
-  if(p(UseBackupMemoryPort)) { io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl }
+  if (p(UseBackupMemoryPort)) { io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl }
+
+  // Memory cache type should be normal non-cacheable bufferable
+  io.mem.map(_.ar.bits.cache := UInt("b0011"))
+  io.mem.map(_.aw.bits.cache := UInt("b0011"))
+
+  // tie off the mmio port
+  val errslave = Module(new NastiErrorSlave)
+  errslave.io <> uncore.io.mmio
 }
 
 /** Wrapper around everything that isn't a Tile.
diff --git a/src/main/scala/TestBench.scala b/src/main/scala/TestBench.scala
new file mode 100644
index 00000000..40800e18
--- /dev/null
+++ b/src/main/scala/TestBench.scala
@@ -0,0 +1,325 @@
+// See LICENSE for license details.
+
+package rocketchip
+
+import Chisel._
+
+object TestBenchGeneration extends FileSystemUtilities {
+  def generateVerilogFragement(
+    topModuleName: String, configClassName: String,
+    nMemChannel: Int) = {
+
+    // YUNSUP:
+    // I originally wrote this using a 2d wire array, but of course Synopsys'
+    // DirectC implementation totally chokes on it when the 2d array is
+    // referenced by the first dimension: the wire shows up as a contiguous
+    // bit collection on the DirectC side.  I had to individually define the
+    // wires.
+
+    val defs = s"""
+  reg htif_out_ready;
+  wire htif_in_valid;
+  wire [`HTIF_WIDTH-1:0] htif_in_bits;
+  wire htif_in_ready, htif_out_valid;
+  wire [`HTIF_WIDTH-1:0] htif_out_bits;
+  wire htif_out_stats;
+
+  wire mem_bk_in_valid;
+  wire mem_bk_out_valid;
+  wire mem_bk_out_ready;
+  wire [`HTIF_WIDTH-1:0] mem_in_bits;
+"""
+    val nasti_defs = (0 until nMemChannel) map { i => s"""
+  wire ar_valid_$i;
+  reg ar_ready_$i;
+  wire [`MEM_ADDR_BITS-1:0] ar_addr_$i;
+  wire [`MEM_ID_BITS-1:0] ar_id_$i;
+  wire [2:0] ar_size_$i;
+  wire [7:0] ar_len_$i;
+
+  wire aw_valid_$i;
+  reg aw_ready_$i;
+  wire [`MEM_ADDR_BITS-1:0] aw_addr_$i;
+  wire [`MEM_ID_BITS-1:0] aw_id_$i;
+  wire [2:0] aw_size_$i;
+  wire [7:0] aw_len_$i;
+
+  wire w_valid_$i;
+  reg w_ready_$i;
+  wire [`MEM_STRB_BITS-1:0] w_strb_$i;
+  wire [`MEM_DATA_BITS-1:0] w_data_$i;
+  wire w_last;
+
+  reg r_valid_$i;
+  wire r_ready_$i;
+  reg [1:0] r_resp_$i;
+  reg [`MEM_ID_BITS-1:0] r_id_$i;
+  reg [`MEM_DATA_BITS-1:0] r_data_$i;
+  reg r_last_$i;
+
+  reg b_valid_$i;
+  wire b_ready_$i;
+  reg [1:0] b_resp_$i;
+  reg [`MEM_ID_BITS-1:0] b_id_$i;
+
+""" } mkString
+
+    val delays = s"""
+  wire htif_clk;
+  wire htif_in_valid_delay;
+  wire htif_in_ready_delay;
+  wire [`HTIF_WIDTH-1:0] htif_in_bits_delay;
+
+  wire htif_out_valid_delay;
+  wire htif_out_ready_delay;
+  wire [`HTIF_WIDTH-1:0] htif_out_bits_delay;
+  
+  wire htif_out_stats_delay;
+
+  wire mem_bk_out_ready_delay;
+  wire mem_bk_in_valid_delay;
+  wire mem_bk_out_valid_delay;
+
+  assign #0.1 htif_in_valid_delay = htif_in_valid;
+  assign #0.1 htif_in_ready = htif_in_ready_delay;
+  assign #0.1 htif_in_bits_delay = htif_in_bits;
+
+  assign #0.1 htif_out_valid = htif_out_valid_delay;
+  assign #0.1 htif_out_ready_delay = htif_out_ready;
+  assign #0.1 htif_out_bits = htif_out_bits_delay;
+  
+  assign #0.1 htif_out_stats = htif_out_stats_delay;
+
+  assign #0.1 mem_bk_out_ready_delay = mem_bk_out_ready;
+  assign #0.1 mem_bk_in_valid_delay = mem_bk_in_valid;
+  assign #0.1 mem_bk_out_valid = mem_bk_out_valid_delay;
+"""
+
+    val nasti_delays = (0 until nMemChannel) map { i => s"""
+  wire ar_valid_delay_$i;
+  wire ar_ready_delay_$i;
+  wire [`MEM_ADDR_BITS-1:0] ar_addr_delay_$i;
+  wire [`MEM_ID_BITS-1:0] ar_id_delay_$i;
+  wire [2:0] ar_size_delay_$i;
+  wire [7:0] ar_len_delay_$i;
+
+  wire aw_valid_delay_$i;
+  wire aw_ready_delay_$i;
+  wire [`MEM_ADDR_BITS-1:0] aw_addr_delay_$i;
+  wire [`MEM_ID_BITS-1:0] aw_id_delay_$i;
+  wire [2:0] aw_size_delay_$i;
+  wire [7:0] aw_len_delay_$i;
+
+  wire w_valid_delay_$i;
+  wire w_ready_delay_$i;
+  wire [`MEM_STRB_BITS-1:0] w_strb_delay_$i;
+  wire [`MEM_DATA_BITS-1:0] w_data_delay_$i;
+  wire w_last_delay_$i;
+
+  wire r_valid_delay_$i;
+  wire r_ready_delay_$i;
+  wire [1:0] r_resp_delay_$i;
+  wire [`MEM_ID_BITS-1:0] r_id_delay_$i;
+  wire [`MEM_DATA_BITS-1:0] r_data_delay_$i;
+  wire r_last_delay_$i;
+
+  wire b_valid_delay_$i;
+  wire b_ready_delay_$i;
+  wire [1:0] b_resp_delay_$i;
+  wire [`MEM_ID_BITS-1:0] b_id_delay_$i;
+
+  assign #0.1 ar_valid_$i = ar_valid_delay_$i;
+  assign #0.1 ar_ready_delay_$i = ar_ready_$i;
+  assign #0.1 ar_addr_$i = ar_addr_delay_$i;
+  assign #0.1 ar_id_$i = ar_id_delay_$i;
+  assign #0.1 ar_size_$i = ar_size_delay_$i;
+  assign #0.1 ar_len_$i = ar_len_delay_$i;
+
+  assign #0.1 aw_valid_$i = aw_valid_delay_$i;
+  assign #0.1 aw_ready_delay_$i = aw_ready_$i;
+  assign #0.1 aw_addr_$i = aw_addr_delay_$i;
+  assign #0.1 aw_id_$i = aw_id_delay_$i;
+  assign #0.1 aw_size_$i = aw_size_delay_$i;
+  assign #0.1 aw_len_$i = aw_len_delay_$i;
+
+  assign #0.1 w_valid_$i = w_valid_delay_$i;
+  assign #0.1 w_ready_delay_$i = w_ready_$i;
+  assign #0.1 w_strb_$i = w_strb_delay_$i;
+  assign #0.1 w_data_$i = w_data_delay_$i;
+  assign #0.1 w_last_$i = w_last_delay_$i;
+
+  assign #0.1 r_valid_delay_$i = r_valid_$i;
+  assign #0.1 r_ready_$i = r_ready_delay_$i;
+  assign #0.1 r_resp_delay_$i = r_resp_$i;
+  assign #0.1 r_id_delay_$i = r_id_$i;
+  assign #0.1 r_data_delay_$i = r_data_$i;
+  assign #0.1 r_last_delay_$i = r_last_$i;
+
+  assign #0.1 b_valid_delay_$i = b_valid_$i;
+  assign #0.1 b_ready_$i = b_ready_delay_$i;
+  assign #0.1 b_resp_delay_$i = b_resp_$i;
+  assign #0.1 b_id_delay_$i = b_id_$i;
+
+""" } mkString
+
+    val nasti_connections = (0 until nMemChannel) map { i => s"""
+    .io_mem_${i}_ar_valid (ar_valid_delay_$i),
+    .io_mem_${i}_ar_ready (ar_ready_delay_$i),
+    .io_mem_${i}_ar_bits_addr (ar_addr_delay_$i),
+    .io_mem_${i}_ar_bits_id (ar_id_delay_$i),
+    .io_mem_${i}_ar_bits_size (ar_size_delay_$i),
+    .io_mem_${i}_ar_bits_len (ar_len_delay_$i),
+    .io_mem_${i}_ar_bits_burst (),
+    .io_mem_${i}_ar_bits_lock (),
+    .io_mem_${i}_ar_bits_cache (),
+    .io_mem_${i}_ar_bits_prot (),
+    .io_mem_${i}_ar_bits_qos (),
+    .io_mem_${i}_ar_bits_region (),
+    .io_mem_${i}_ar_bits_user (),
+
+    .io_mem_${i}_aw_valid (aw_valid_delay_$i),
+    .io_mem_${i}_aw_ready (aw_ready_delay_$i),
+    .io_mem_${i}_aw_bits_addr (aw_addr_delay_$i),
+    .io_mem_${i}_aw_bits_id (aw_id_delay_$i),
+    .io_mem_${i}_aw_bits_size (aw_size_delay_$i),
+    .io_mem_${i}_aw_bits_len (aw_len_delay_$i),
+    .io_mem_${i}_aw_bits_burst (),
+    .io_mem_${i}_aw_bits_lock (),
+    .io_mem_${i}_aw_bits_cache (),
+    .io_mem_${i}_aw_bits_prot (),
+    .io_mem_${i}_aw_bits_qos (),
+    .io_mem_${i}_aw_bits_region (),
+    .io_mem_${i}_aw_bits_user (),
+
+    .io_mem_${i}_w_valid (w_valid_delay_$i),
+    .io_mem_${i}_w_ready (w_ready_delay_$i),
+    .io_mem_${i}_w_bits_strb (w_strb_delay_$i),
+    .io_mem_${i}_w_bits_data (w_data_delay_$i),
+    .io_mem_${i}_w_bits_last (w_last_delay_$i),
+    .io_mem_${i}_w_bits_user (),
+
+    .io_mem_${i}_r_valid (r_valid_delay_$i),
+    .io_mem_${i}_r_ready (r_ready_delay_$i),
+    .io_mem_${i}_r_bits_resp (r_resp_delay_$i),
+    .io_mem_${i}_r_bits_id (r_id_delay_$i),
+    .io_mem_${i}_r_bits_data (r_data_delay_$i),
+    .io_mem_${i}_r_bits_last (r_last_delay_$i),
+    .io_mem_${i}_r_bits_user (1'b0),
+
+    .io_mem_${i}_b_valid (b_valid_delay_$i),
+    .io_mem_${i}_b_ready (b_ready_delay_$i),
+    .io_mem_${i}_b_bits_resp (b_resp_delay_$i),
+    .io_mem_${i}_b_bits_id (b_id_delay_$i),
+    .io_mem_${i}_b_bits_user (1'b0),
+
+""" } mkString
+
+    val instantiation = s"""
+`ifdef FPGA
+  assign mem_bk_out_valid_delay = 1'b0;
+  assign htif_out_stats_delay = 1'b0;
+  assign htif_clk = clk;
+`endif
+
+  Top dut
+  (
+    .clk(clk),
+    .reset(reset),
+
+    $nasti_connections
+
+`ifndef FPGA
+    .io_host_clk(htif_clk),
+    .io_host_clk_edge(),
+    .io_host_debug_stats_csr(htif_out_stats_delay),
+
+`ifdef MEM_BACKUP_EN
+    .io_mem_backup_ctrl_en(1'b1),
+`else
+    .io_mem_backup_ctrl_en(1'b0),
+`endif // MEM_BACKUP_EN
+    .io_mem_backup_ctrl_in_valid(mem_bk_in_valid_delay),
+    .io_mem_backup_ctrl_out_ready(mem_bk_out_ready_delay),
+    .io_mem_backup_ctrl_out_valid(mem_bk_out_valid_delay),
+`else
+    .io_host_clk (),
+    .io_host_clk_edge (),
+    .io_host_debug_stats_csr (),
+
+    .io_mem_backup_ctrl_en (1'b0),
+    .io_mem_backup_ctrl_in_valid (1'b0),
+    .io_mem_backup_ctrl_out_ready (1'b0),
+    .io_mem_backup_ctrl_out_valid (),
+`endif // FPGA
+
+    .io_host_in_valid(htif_in_valid_delay),
+    .io_host_in_ready(htif_in_ready_delay),
+    .io_host_in_bits(htif_in_bits_delay),
+    .io_host_out_valid(htif_out_valid_delay),
+    .io_host_out_ready(htif_out_ready_delay),
+    .io_host_out_bits(htif_out_bits_delay)
+  );
+"""
+
+    val ticks = (0 until nMemChannel) map { i => s"""
+  reg [31:0] channel_$i = $i;
+
+  always @(posedge clk)
+  begin
+    if (reset || r_reset)
+    begin
+      ar_ready_$i <= 1'b0;
+      aw_ready_$i <= 1'b0;
+      w_ready_$i <= 1'b0;
+      r_valid_$i <= 1'b0;
+      r_resp_$i <= 2'b0;
+      r_id_$i <= {`MEM_ID_BITS {1'b0}};
+      r_data_$i <= {`MEM_DATA_BITS {1'b0}};
+      r_last_$i <= 1'b0;
+      b_valid_$i <= 1'b0;
+      b_resp_$i <= 2'b0;
+      b_id_$i <= {`MEM_ID_BITS {1'b0}};
+    end
+    else
+    begin
+      memory_tick
+      (
+        channel_$i,
+        ar_valid_$i, ar_ready_$i, ar_addr_$i, ar_id_$i, ar_size_$i, ar_len_$i,
+        aw_valid_$i, aw_ready_$i, aw_addr_$i, aw_id_$i, aw_size_$i, aw_len_$i,
+        w_valid_$i, w_ready_$i, w_strb_$i, w_data_$i, w_last_$i,
+        r_valid_$i, r_ready_$i, r_resp_$i, r_id_$i, r_data_$i, r_last_$i,
+        b_valid_$i, b_ready_$i, b_resp_$i, b_id_$i
+      );
+    end
+  end
+
+  always @(posedge clk)
+  begin
+    if (verbose)
+    begin
+      if (ar_valid_$i && ar_ready_$i)
+      begin
+        $$fdisplay(stderr, "MC$i: ar addr=%x", ar_addr_$i);
+      end
+      if (aw_valid_$i && aw_ready_$i)
+      begin
+        $$fdisplay(stderr, "MC$i: aw addr=%x", aw_addr_$i);
+      end
+      if (w_valid_$i && w_ready_$i)
+      begin
+        $$fdisplay(stderr, "MC$i: w data=%x", w_data_$i);
+      end
+      if (r_valid_$i && r_ready_$i)
+      begin
+        $$fdisplay(stderr, "MC$i: r data=%x", r_data_$i);
+      end
+    end
+  end
+""" } mkString
+
+    val f = createOutputFile(s"$topModuleName.$configClassName.tb.vfrag")
+    f.write(defs + nasti_defs + delays + nasti_delays + instantiation + ticks)
+    f.close
+  }
+}
diff --git a/src/main/scala/Testing.scala b/src/main/scala/Testing.scala
index 7aea6116..df66abf4 100644
--- a/src/main/scala/Testing.scala
+++ b/src/main/scala/Testing.scala
@@ -152,6 +152,9 @@ object TestGenerator extends App with FileSystemUtilities {
   //Driver.elaborate(gen, configName = configClassName)
 
   TestGeneration.generateMakefrag(topModuleName, configClassName)
+  TestBenchGeneration.generateVerilogFragement(
+    topModuleName, configClassName,
+    paramsFromConfig(NMemoryChannels))
 
   val pdFile = createOutputFile(s"$topModuleName.$configClassName.prm")
   pdFile.write(ParameterDump.getDump)
diff --git a/vsim/Makefrag b/vsim/Makefrag
index a1f91b11..236e5d3e 100644
--- a/vsim/Makefrag
+++ b/vsim/Makefrag
@@ -42,6 +42,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	-e vcs_main \
 	$(RISCV)/lib/libfesvr.so \
 	$(sim_dir)/libdramsim.a \
+	+incdir+$(generated_dir) \
 	+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
 	+define+PRINTF_COND=$(TB).verbose \
 	+libext+.v \
diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog
index cc553505..39ed5472 100644
--- a/vsim/Makefrag-verilog
+++ b/vsim/Makefrag-verilog
@@ -13,6 +13,7 @@ $(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).v
 	echo "\`ifndef CONST_VH" > $@
 	echo "\`define CONST_VH" >> $@
 	sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $(patsubst %.v,%.prm,$<) >> $@
+	echo "\`define TBVFRAG \"$(MODEL).$(CONFIG).tb.vfrag\"" >> $@
 	echo "\`endif // CONST_VH" >> $@
 
 $(generated_dir)/memdessertMemDessert.$(CONFIG).v $(generated_dir)/memdessertMemDessert.$(CONFIG).d: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
diff --git a/vsrc/rocketTestHarness.v b/vsrc/rocketTestHarness.v
index ea3d9d55..42aa720d 100644
--- a/vsrc/rocketTestHarness.v
+++ b/vsrc/rocketTestHarness.v
@@ -2,6 +2,7 @@
 
 extern "A" void htif_init
 (
+  input reg [31:0] n_mem_channel,
   input reg [31:0] htif_width,
   input reg [31:0] mem_width
 );
@@ -23,6 +24,8 @@ extern "A" void htif_tick
 
 extern "A" void memory_tick
 (
+  input  reg [31:0]               channel,
+
   input  reg                      ar_valid,
   output reg                      ar_ready,
   input  reg [`MEM_ADDR_BITS-1:0] ar_addr,
@@ -71,249 +74,24 @@ module rocketTestHarness;
 
   always #`CLOCK_PERIOD clk = ~clk;
 
-  wire ar_valid;
-  reg ar_ready;
-  wire [`MEM_ADDR_BITS-1:0] ar_addr;
-  wire [`MEM_ID_BITS-1:0] ar_id;
-  wire [2:0] ar_size;
-  wire [7:0] ar_len;
+  reg [  31:0] n_mem_channel = `N_MEM_CHANNELS;
+  reg [  31:0] htif_width = `HTIF_WIDTH;
+  reg [  31:0] mem_width = `MEM_DATA_BITS;
+  reg [  63:0] max_cycles = 0;
+  reg [  63:0] trace_count = 0;
+  reg [1023:0] loadmem = 0;
+  reg [1023:0] vcdplusfile = 0;
+  reg [1023:0] vcdfile = 0;
+  reg          stats_active = 0;
+  reg          stats_tracking = 0;
+  reg          verbose = 0;
+  integer      stderr = 32'h80000002;
 
-  wire aw_valid;
-  reg aw_ready;
-  wire [`MEM_ADDR_BITS-1:0] aw_addr;
-  wire [`MEM_ID_BITS-1:0] aw_id;
-  wire [2:0] aw_size;
-  wire [7:0] aw_len;
+`include `TBVFRAG
 
-  wire w_valid;
-  reg w_ready;
-  wire [`MEM_STRB_BITS-1:0] w_strb;
-  wire [`MEM_DATA_BITS-1:0] w_data;
-  wire w_last;
-
-  reg r_valid;
-  wire r_ready;
-  reg [1:0] r_resp;
-  reg [`MEM_ID_BITS-1:0] r_id;
-  reg [`MEM_DATA_BITS-1:0] r_data;
-  reg r_last;
-
-  reg b_valid;
-  wire b_ready;
-  reg [1:0] b_resp;
-  reg [`MEM_ID_BITS-1:0] b_id;
-
-  reg htif_out_ready;
-  wire htif_in_valid;
-  wire [`HTIF_WIDTH-1:0] htif_in_bits;
-  wire htif_in_ready, htif_out_valid;
-  wire [`HTIF_WIDTH-1:0] htif_out_bits;
-  wire htif_out_stats;
-
-  wire mem_bk_in_valid;
-  wire mem_bk_out_valid;
-  wire mem_bk_out_ready;
-  wire [`HTIF_WIDTH-1:0] mem_in_bits;
-
-  wire htif_clk;
-  wire #0.1 htif_in_valid_delay = htif_in_valid;
-  wire htif_in_ready_delay; assign #0.1 htif_in_ready = htif_in_ready_delay;
-  wire [`HTIF_WIDTH-1:0] #0.1 htif_in_bits_delay = htif_in_bits;
-
-  wire htif_out_valid_delay; assign #0.1 htif_out_valid = htif_out_valid_delay;
-  wire #0.1 htif_out_ready_delay = htif_out_ready;
-  wire [`HTIF_WIDTH-1:0] htif_out_bits_delay; assign #0.1 htif_out_bits = htif_out_bits_delay;
-  
-  wire htif_out_stats_delay; assign #0.1 htif_out_stats = htif_out_stats_delay;
-
-  wire ar_valid_delay; assign #0.1 ar_valid = ar_valid_delay;
-  wire #0.1 ar_ready_delay = ar_ready;
-  wire [`MEM_ADDR_BITS-1:0] ar_addr_delay; assign #0.1 ar_addr = ar_addr_delay;
-  wire [`MEM_ID_BITS-1:0] ar_id_delay; assign #0.1 ar_id = ar_id_delay;
-  wire [2:0] ar_size_delay; assign #0.1 ar_size = ar_size_delay;
-  wire [7:0] ar_len_delay; assign #0.1 ar_len = ar_len_delay;
-
-  wire aw_valid_delay; assign #0.1 aw_valid = aw_valid_delay;
-  wire #0.1 aw_ready_delay = aw_ready;
-  wire [`MEM_ADDR_BITS-1:0] aw_addr_delay; assign #0.1 aw_addr = aw_addr_delay;
-  wire [`MEM_ID_BITS-1:0] aw_id_delay; assign #0.1 aw_id = aw_id_delay;
-  wire [2:0] aw_size_delay; assign #0.1 aw_size = aw_size_delay;
-  wire [7:0] aw_len_delay; assign #0.1 aw_len = aw_len_delay;
-
-  wire w_valid_delay; assign #0.1 w_valid = w_valid_delay;
-  wire #0.1 w_ready_delay = w_ready;
-  wire [`MEM_STRB_BITS-1:0] w_strb_delay; assign #0.1 w_strb = w_strb_delay;
-  wire [`MEM_DATA_BITS-1:0] w_data_delay; assign #0.1 w_data = w_data_delay;
-  wire w_last_delay; assign #0.1 w_last = w_last_delay;
-
-  wire #0.1 r_valid_delay = r_valid;
-  wire r_ready_delay; assign #0.1 r_ready = r_ready_delay;
-  wire [1:0] #0.1 r_resp_delay = r_resp;
-  wire [`MEM_ID_BITS-1:0] #0.1 r_id_delay = r_id;
-  wire [`MEM_DATA_BITS-1:0] #0.1 r_data_delay = r_data;
-  wire #0.1 r_last_delay = r_last;
-
-  wire #0.1 b_valid_delay = b_valid;
-  wire b_ready_delay; assign #0.1 b_ready = b_ready_delay;
-  wire [1:0] #0.1 b_resp_delay = b_resp;
-  wire [`MEM_ID_BITS-1:0] #0.1 b_id_delay = b_id;
-
-  wire #0.1 mem_bk_out_ready_delay = mem_bk_out_ready;
-  wire #0.1 mem_bk_in_valid_delay = mem_bk_in_valid;
-  wire mem_bk_out_valid_delay; assign #0.1 mem_bk_out_valid = mem_bk_out_valid_delay;
-
-`ifdef FPGA
-  assign mem_bk_out_valid_delay = 1'b0;
-  assign htif_out_stats_delay = 1'b0;
-`endif
-
-  Top dut
-  (
-    .clk(clk),
-    .reset(reset),
-
-    .io_host_in_valid(htif_in_valid_delay),
-    .io_host_in_ready(htif_in_ready_delay),
-    .io_host_in_bits(htif_in_bits_delay),
-    .io_host_out_valid(htif_out_valid_delay),
-    .io_host_out_ready(htif_out_ready_delay),
-    .io_host_out_bits(htif_out_bits_delay),
-
-`ifndef FPGA
-    .io_host_clk(htif_clk),
-    .io_host_clk_edge(),
-    .io_host_debug_stats_csr(htif_out_stats_delay),
-
-`ifdef MEM_BACKUP_EN
-    .io_mem_backup_ctrl_en(1'b1),
-`else
-    .io_mem_backup_ctrl_en(1'b0),
-`endif // MEM_BACKUP_EN
-    .io_mem_backup_ctrl_in_valid(mem_bk_in_valid_delay),
-    .io_mem_backup_ctrl_out_ready(mem_bk_out_ready_delay),
-    .io_mem_backup_ctrl_out_valid(mem_bk_out_valid_delay),
-`else
-    .io_host_clk (),
-    .io_host_clk_edge (),
-    .io_host_debug_stats_csr (),
-
-    .io_mem_backup_ctrl_en (1'b0),
-    .io_mem_backup_ctrl_in_valid (1'b0),
-    .io_mem_backup_ctrl_out_ready (1'b0),
-    .io_mem_backup_ctrl_out_valid (),
-`endif // FPGA
-
-    .io_mem_ar_valid (ar_valid_delay),
-    .io_mem_ar_ready (ar_ready_delay),
-    .io_mem_ar_bits_addr (ar_addr_delay),
-    .io_mem_ar_bits_id (ar_id_delay),
-    .io_mem_ar_bits_size (ar_size_delay),
-    .io_mem_ar_bits_len (ar_len_delay),
-    .io_mem_ar_bits_burst (),
-    .io_mem_ar_bits_lock (),
-    .io_mem_ar_bits_cache (),
-    .io_mem_ar_bits_prot (),
-    .io_mem_ar_bits_qos (),
-    .io_mem_ar_bits_region (),
-    .io_mem_ar_bits_user (),
-
-    .io_mem_aw_valid (aw_valid_delay),
-    .io_mem_aw_ready (aw_ready_delay),
-    .io_mem_aw_bits_addr (aw_addr_delay),
-    .io_mem_aw_bits_id (aw_id_delay),
-    .io_mem_aw_bits_size (aw_size_delay),
-    .io_mem_aw_bits_len (aw_len_delay),
-    .io_mem_aw_bits_burst (),
-    .io_mem_aw_bits_lock (),
-    .io_mem_aw_bits_cache (),
-    .io_mem_aw_bits_prot (),
-    .io_mem_aw_bits_qos (),
-    .io_mem_aw_bits_region (),
-    .io_mem_aw_bits_user (),
-
-    .io_mem_w_valid (w_valid_delay),
-    .io_mem_w_ready (w_ready_delay),
-    .io_mem_w_bits_strb (w_strb_delay),
-    .io_mem_w_bits_data (w_data_delay),
-    .io_mem_w_bits_last (w_last_delay),
-    .io_mem_w_bits_user (),
-
-    .io_mem_r_valid (r_valid_delay),
-    .io_mem_r_ready (r_ready_delay),
-    .io_mem_r_bits_resp (r_resp_delay),
-    .io_mem_r_bits_id (r_id_delay),
-    .io_mem_r_bits_data (r_data_delay),
-    .io_mem_r_bits_last (r_last_delay),
-    .io_mem_r_bits_user (1'b0),
-
-    .io_mem_b_valid (b_valid_delay),
-    .io_mem_b_ready (b_ready_delay),
-    .io_mem_b_bits_resp (b_resp_delay),
-    .io_mem_b_bits_id (b_id_delay),
-    .io_mem_b_bits_user (1'b0)
-  );
-  
-`ifdef FPGA
-  assign htif_clk = clk;
-`endif
-
-  //-----------------------------------------------
-  // Memory interface
-
-  always @(negedge clk)
+  always @(posedge clk)
   begin
     r_reset <= reset;
-    if (reset || r_reset)
-    begin
-      ar_ready <= 1'b0;
-      aw_ready <= 1'b0;
-      w_ready <= 1'b0;
-      r_valid <= 1'b0;
-      r_resp <= 2'b0;
-      r_id <= {`MEM_ID_BITS {1'b0}};
-      r_data <= {`MEM_DATA_BITS {1'b0}};
-      r_last <= 1'b0;
-      b_valid <= 1'b0;
-      b_resp <= 2'b0;
-      b_id <= {`MEM_ID_BITS {1'b0}};
-    end
-    else
-    begin
-      memory_tick
-      (
-        ar_valid,
-        ar_ready,
-        ar_addr,
-        ar_id,
-        ar_size,
-        ar_len,
-
-        aw_valid,
-        aw_ready,
-        aw_addr,
-        aw_id,
-        aw_size,
-        aw_len,
-
-        w_valid,
-        w_ready,
-        w_strb,
-        w_data,
-        w_last,
-
-        r_valid,
-        r_ready,
-        r_resp,
-        r_id,
-        r_data,
-        r_last,
-
-        b_valid,
-        b_ready,
-        b_resp,
-        b_id
-      );
-    end
   end
 
   wire mem_bk_req_valid, mem_bk_req_rw, mem_bk_req_data_valid;
@@ -418,17 +196,6 @@ module rocketTestHarness;
 
   //-----------------------------------------------
   // Start the simulation
-  reg [  31:0] htif_width = `HTIF_WIDTH;
-  reg [  31:0] mem_width = `MEM_DATA_BITS;
-  reg [  63:0] max_cycles = 0;
-  reg [  63:0] trace_count = 0;
-  reg [1023:0] loadmem = 0;
-  reg [1023:0] vcdplusfile = 0;
-  reg [1023:0] vcdfile = 0;
-  reg          stats_active = 0;
-  reg          stats_tracking = 0;
-  reg          verbose = 0;
-  integer      stderr = 32'h80000002;
 
   // Some helper functions for turning on, stopping, and finishing stat tracking
   task start_stats;
@@ -474,7 +241,7 @@ module rocketTestHarness;
       $readmemh(loadmem, mem.ram);
 `endif
     verbose = $test$plusargs("verbose");
-    htif_init(htif_width, mem_width);
+    htif_init(n_mem_channel, htif_width, mem_width);
 `ifdef DEBUG
     stats_active = $test$plusargs("stats");
     if ($value$plusargs("vcdplusfile=%s", vcdplusfile))
@@ -552,29 +319,6 @@ module rocketTestHarness;
     end
   end
 
-  always @(posedge clk)
-  begin
-    if (verbose)
-    begin
-      if (ar_valid && ar_ready)
-      begin
-        $fdisplay(stderr, "MC: ar addr=%x", ar_addr);
-      end
-      if (aw_valid && aw_ready)
-      begin
-        $fdisplay(stderr, "MC: aw addr=%x", aw_addr);
-      end
-      if (w_valid && w_ready)
-      begin
-        $fdisplay(stderr, "MC: w data=%x", w_data);
-      end
-      if (r_valid && r_ready)
-      begin
-        $fdisplay(stderr, "MC: r data=%x", r_data);
-      end
-    end
-  end
-
   always @(posedge clk)
   begin
     trace_count = trace_count + 1;