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add multichannel NASTI support in Verilog testbench

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This commit is contained in:
Yunsup Lee
2015-10-30 21:14:33 -07:00
committed by Howard Mao
parent 9dabcab9c2
commit 0d245741bc
10 changed files with 446 additions and 376 deletions
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4
src/main/scala/Configs.scala
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@ -154,11 +154,11 @@ class DefaultConfig extends Config (
dataBits = site(CacheBlockBytes)*8)
case TLKey("Outermost") => site(TLKey("L2toMC")).copy(dataBeats = site(MIFDataBeats))
case NTiles => Knob("NTILES")
case NMemoryChannels => 1
case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
case NBanksPerMemoryChannel => Knob("NBANKS")
case NOutstandingMemReqsPerChannel => site(NBanksPerMemoryChannel)*(site(NAcquireTransactors)+2)
case BankIdLSB => 0
case CacheBlockBytes => 64
case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
case UseBackupMemoryPort => true
case MMIOBase => BigInt(1 << 30) // 1 GB

39
src/main/scala/RocketChip.scala
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@ -68,12 +68,7 @@ class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
}
class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
val mem = new NastiIO
}
class MultiChannelTopIO(implicit p: Parameters) extends BasicTopIO()(p) {
val mem = Vec(new NastiIO, nMemChannels)
val mmio = new NastiIO
}
object TopUtils {
@ -94,29 +89,6 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
implicit val p = topParams
val io = new TopIO
val temp = Module(new MultiChannelTop)
val arb = Module(new NastiArbiter(nMemChannels))
arb.io.master <> temp.io.mem
io.mem.ar <> Queue(arb.io.slave.ar)
io.mem.aw <> Queue(arb.io.slave.aw)
io.mem.w <> Queue(arb.io.slave.w)
arb.io.slave.r <> Queue(io.mem.r)
arb.io.slave.b <> Queue(io.mem.b)
io.mem_backup_ctrl <> temp.io.mem_backup_ctrl
io.host <> temp.io.host
// Memory cache type should be normal non-cacheable bufferable
io.mem.ar.bits.cache := UInt("b0011")
io.mem.aw.bits.cache := UInt("b0011")
// tie off the mmio port
val errslave = Module(new NastiErrorSlave)
errslave.io <> temp.io.mmio
}
class MultiChannelTop(implicit val p: Parameters) extends Module with HasTopLevelParameters {
val io = new MultiChannelTopIO
// Build an Uncore and a set of Tiles
val innerTLParams = p.alterPartial({case TLId => "L1toL2" })
val uncore = Module(new Uncore()(innerTLParams))
@ -139,8 +111,15 @@ class MultiChannelTop(implicit val p: Parameters) extends Module with HasTopLeve
uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten
io.host <> uncore.io.host
io.mem <> uncore.io.mem
io.mmio <> uncore.io.mmio
if(p(UseBackupMemoryPort)) { io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl }
if (p(UseBackupMemoryPort)) { io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl }
// Memory cache type should be normal non-cacheable bufferable
io.mem.map(_.ar.bits.cache := UInt("b0011"))
io.mem.map(_.aw.bits.cache := UInt("b0011"))
// tie off the mmio port
val errslave = Module(new NastiErrorSlave)
errslave.io <> uncore.io.mmio
}
/** Wrapper around everything that isn't a Tile.

325
src/main/scala/TestBench.scala Normal file
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@ -0,0 +1,325 @@
// See LICENSE for license details.
package rocketchip
import Chisel._
object TestBenchGeneration extends FileSystemUtilities {
def generateVerilogFragement(
topModuleName: String, configClassName: String,
nMemChannel: Int) = {
// YUNSUP:
// I originally wrote this using a 2d wire array, but of course Synopsys'
// DirectC implementation totally chokes on it when the 2d array is
// referenced by the first dimension: the wire shows up as a contiguous
// bit collection on the DirectC side. I had to individually define the
// wires.
val defs = s"""
reg htif_out_ready;
wire htif_in_valid;
wire [`HTIF_WIDTH-1:0] htif_in_bits;
wire htif_in_ready, htif_out_valid;
wire [`HTIF_WIDTH-1:0] htif_out_bits;
wire htif_out_stats;
wire mem_bk_in_valid;
wire mem_bk_out_valid;
wire mem_bk_out_ready;
wire [`HTIF_WIDTH-1:0] mem_in_bits;
"""
val nasti_defs = (0 until nMemChannel) map { i => s"""
wire ar_valid_$i;
reg ar_ready_$i;
wire [`MEM_ADDR_BITS-1:0] ar_addr_$i;
wire [`MEM_ID_BITS-1:0] ar_id_$i;
wire [2:0] ar_size_$i;
wire [7:0] ar_len_$i;
wire aw_valid_$i;
reg aw_ready_$i;
wire [`MEM_ADDR_BITS-1:0] aw_addr_$i;
wire [`MEM_ID_BITS-1:0] aw_id_$i;
wire [2:0] aw_size_$i;
wire [7:0] aw_len_$i;
wire w_valid_$i;
reg w_ready_$i;
wire [`MEM_STRB_BITS-1:0] w_strb_$i;
wire [`MEM_DATA_BITS-1:0] w_data_$i;
wire w_last;
reg r_valid_$i;
wire r_ready_$i;
reg [1:0] r_resp_$i;
reg [`MEM_ID_BITS-1:0] r_id_$i;
reg [`MEM_DATA_BITS-1:0] r_data_$i;
reg r_last_$i;
reg b_valid_$i;
wire b_ready_$i;
reg [1:0] b_resp_$i;
reg [`MEM_ID_BITS-1:0] b_id_$i;
""" } mkString
val delays = s"""
wire htif_clk;
wire htif_in_valid_delay;
wire htif_in_ready_delay;
wire [`HTIF_WIDTH-1:0] htif_in_bits_delay;
wire htif_out_valid_delay;
wire htif_out_ready_delay;
wire [`HTIF_WIDTH-1:0] htif_out_bits_delay;
wire htif_out_stats_delay;
wire mem_bk_out_ready_delay;
wire mem_bk_in_valid_delay;
wire mem_bk_out_valid_delay;
assign #0.1 htif_in_valid_delay = htif_in_valid;
assign #0.1 htif_in_ready = htif_in_ready_delay;
assign #0.1 htif_in_bits_delay = htif_in_bits;
assign #0.1 htif_out_valid = htif_out_valid_delay;
assign #0.1 htif_out_ready_delay = htif_out_ready;
assign #0.1 htif_out_bits = htif_out_bits_delay;
assign #0.1 htif_out_stats = htif_out_stats_delay;
assign #0.1 mem_bk_out_ready_delay = mem_bk_out_ready;
assign #0.1 mem_bk_in_valid_delay = mem_bk_in_valid;
assign #0.1 mem_bk_out_valid = mem_bk_out_valid_delay;
"""
val nasti_delays = (0 until nMemChannel) map { i => s"""
wire ar_valid_delay_$i;
wire ar_ready_delay_$i;
wire [`MEM_ADDR_BITS-1:0] ar_addr_delay_$i;
wire [`MEM_ID_BITS-1:0] ar_id_delay_$i;
wire [2:0] ar_size_delay_$i;
wire [7:0] ar_len_delay_$i;
wire aw_valid_delay_$i;
wire aw_ready_delay_$i;
wire [`MEM_ADDR_BITS-1:0] aw_addr_delay_$i;
wire [`MEM_ID_BITS-1:0] aw_id_delay_$i;
wire [2:0] aw_size_delay_$i;
wire [7:0] aw_len_delay_$i;
wire w_valid_delay_$i;
wire w_ready_delay_$i;
wire [`MEM_STRB_BITS-1:0] w_strb_delay_$i;
wire [`MEM_DATA_BITS-1:0] w_data_delay_$i;
wire w_last_delay_$i;
wire r_valid_delay_$i;
wire r_ready_delay_$i;
wire [1:0] r_resp_delay_$i;
wire [`MEM_ID_BITS-1:0] r_id_delay_$i;
wire [`MEM_DATA_BITS-1:0] r_data_delay_$i;
wire r_last_delay_$i;
wire b_valid_delay_$i;
wire b_ready_delay_$i;
wire [1:0] b_resp_delay_$i;
wire [`MEM_ID_BITS-1:0] b_id_delay_$i;
assign #0.1 ar_valid_$i = ar_valid_delay_$i;
assign #0.1 ar_ready_delay_$i = ar_ready_$i;
assign #0.1 ar_addr_$i = ar_addr_delay_$i;
assign #0.1 ar_id_$i = ar_id_delay_$i;
assign #0.1 ar_size_$i = ar_size_delay_$i;
assign #0.1 ar_len_$i = ar_len_delay_$i;
assign #0.1 aw_valid_$i = aw_valid_delay_$i;
assign #0.1 aw_ready_delay_$i = aw_ready_$i;
assign #0.1 aw_addr_$i = aw_addr_delay_$i;
assign #0.1 aw_id_$i = aw_id_delay_$i;
assign #0.1 aw_size_$i = aw_size_delay_$i;
assign #0.1 aw_len_$i = aw_len_delay_$i;
assign #0.1 w_valid_$i = w_valid_delay_$i;
assign #0.1 w_ready_delay_$i = w_ready_$i;
assign #0.1 w_strb_$i = w_strb_delay_$i;
assign #0.1 w_data_$i = w_data_delay_$i;
assign #0.1 w_last_$i = w_last_delay_$i;
assign #0.1 r_valid_delay_$i = r_valid_$i;
assign #0.1 r_ready_$i = r_ready_delay_$i;
assign #0.1 r_resp_delay_$i = r_resp_$i;
assign #0.1 r_id_delay_$i = r_id_$i;
assign #0.1 r_data_delay_$i = r_data_$i;
assign #0.1 r_last_delay_$i = r_last_$i;
assign #0.1 b_valid_delay_$i = b_valid_$i;
assign #0.1 b_ready_$i = b_ready_delay_$i;
assign #0.1 b_resp_delay_$i = b_resp_$i;
assign #0.1 b_id_delay_$i = b_id_$i;
""" } mkString
val nasti_connections = (0 until nMemChannel) map { i => s"""
.io_mem_${i}_ar_valid (ar_valid_delay_$i),
.io_mem_${i}_ar_ready (ar_ready_delay_$i),
.io_mem_${i}_ar_bits_addr (ar_addr_delay_$i),
.io_mem_${i}_ar_bits_id (ar_id_delay_$i),
.io_mem_${i}_ar_bits_size (ar_size_delay_$i),
.io_mem_${i}_ar_bits_len (ar_len_delay_$i),
.io_mem_${i}_ar_bits_burst (),
.io_mem_${i}_ar_bits_lock (),
.io_mem_${i}_ar_bits_cache (),
.io_mem_${i}_ar_bits_prot (),
.io_mem_${i}_ar_bits_qos (),
.io_mem_${i}_ar_bits_region (),
.io_mem_${i}_ar_bits_user (),
.io_mem_${i}_aw_valid (aw_valid_delay_$i),
.io_mem_${i}_aw_ready (aw_ready_delay_$i),
.io_mem_${i}_aw_bits_addr (aw_addr_delay_$i),
.io_mem_${i}_aw_bits_id (aw_id_delay_$i),
.io_mem_${i}_aw_bits_size (aw_size_delay_$i),
.io_mem_${i}_aw_bits_len (aw_len_delay_$i),
.io_mem_${i}_aw_bits_burst (),
.io_mem_${i}_aw_bits_lock (),
.io_mem_${i}_aw_bits_cache (),
.io_mem_${i}_aw_bits_prot (),
.io_mem_${i}_aw_bits_qos (),
.io_mem_${i}_aw_bits_region (),
.io_mem_${i}_aw_bits_user (),
.io_mem_${i}_w_valid (w_valid_delay_$i),
.io_mem_${i}_w_ready (w_ready_delay_$i),
.io_mem_${i}_w_bits_strb (w_strb_delay_$i),
.io_mem_${i}_w_bits_data (w_data_delay_$i),
.io_mem_${i}_w_bits_last (w_last_delay_$i),
.io_mem_${i}_w_bits_user (),
.io_mem_${i}_r_valid (r_valid_delay_$i),
.io_mem_${i}_r_ready (r_ready_delay_$i),
.io_mem_${i}_r_bits_resp (r_resp_delay_$i),
.io_mem_${i}_r_bits_id (r_id_delay_$i),
.io_mem_${i}_r_bits_data (r_data_delay_$i),
.io_mem_${i}_r_bits_last (r_last_delay_$i),
.io_mem_${i}_r_bits_user (1'b0),
.io_mem_${i}_b_valid (b_valid_delay_$i),
.io_mem_${i}_b_ready (b_ready_delay_$i),
.io_mem_${i}_b_bits_resp (b_resp_delay_$i),
.io_mem_${i}_b_bits_id (b_id_delay_$i),
.io_mem_${i}_b_bits_user (1'b0),
""" } mkString
val instantiation = s"""
`ifdef FPGA
assign mem_bk_out_valid_delay = 1'b0;
assign htif_out_stats_delay = 1'b0;
assign htif_clk = clk;
`endif
Top dut
(
.clk(clk),
.reset(reset),
$nasti_connections
`ifndef FPGA
.io_host_clk(htif_clk),
.io_host_clk_edge(),
.io_host_debug_stats_csr(htif_out_stats_delay),
`ifdef MEM_BACKUP_EN
.io_mem_backup_ctrl_en(1'b1),
`else
.io_mem_backup_ctrl_en(1'b0),
`endif // MEM_BACKUP_EN
.io_mem_backup_ctrl_in_valid(mem_bk_in_valid_delay),
.io_mem_backup_ctrl_out_ready(mem_bk_out_ready_delay),
.io_mem_backup_ctrl_out_valid(mem_bk_out_valid_delay),
`else
.io_host_clk (),
.io_host_clk_edge (),
.io_host_debug_stats_csr (),
.io_mem_backup_ctrl_en (1'b0),
.io_mem_backup_ctrl_in_valid (1'b0),
.io_mem_backup_ctrl_out_ready (1'b0),
.io_mem_backup_ctrl_out_valid (),
`endif // FPGA
.io_host_in_valid(htif_in_valid_delay),
.io_host_in_ready(htif_in_ready_delay),
.io_host_in_bits(htif_in_bits_delay),
.io_host_out_valid(htif_out_valid_delay),
.io_host_out_ready(htif_out_ready_delay),
.io_host_out_bits(htif_out_bits_delay)
);
"""
val ticks = (0 until nMemChannel) map { i => s"""
reg [31:0] channel_$i = $i;
always @(posedge clk)
begin
if (reset || r_reset)
begin
ar_ready_$i <= 1'b0;
aw_ready_$i <= 1'b0;
w_ready_$i <= 1'b0;
r_valid_$i <= 1'b0;
r_resp_$i <= 2'b0;
r_id_$i <= {`MEM_ID_BITS {1'b0}};
r_data_$i <= {`MEM_DATA_BITS {1'b0}};
r_last_$i <= 1'b0;
b_valid_$i <= 1'b0;
b_resp_$i <= 2'b0;
b_id_$i <= {`MEM_ID_BITS {1'b0}};
end
else
begin
memory_tick
(
channel_$i,
ar_valid_$i, ar_ready_$i, ar_addr_$i, ar_id_$i, ar_size_$i, ar_len_$i,
aw_valid_$i, aw_ready_$i, aw_addr_$i, aw_id_$i, aw_size_$i, aw_len_$i,
w_valid_$i, w_ready_$i, w_strb_$i, w_data_$i, w_last_$i,
r_valid_$i, r_ready_$i, r_resp_$i, r_id_$i, r_data_$i, r_last_$i,
b_valid_$i, b_ready_$i, b_resp_$i, b_id_$i
);
end
end
always @(posedge clk)
begin
if (verbose)
begin
if (ar_valid_$i && ar_ready_$i)
begin
$$fdisplay(stderr, "MC$i: ar addr=%x", ar_addr_$i);
end
if (aw_valid_$i && aw_ready_$i)
begin
$$fdisplay(stderr, "MC$i: aw addr=%x", aw_addr_$i);
end
if (w_valid_$i && w_ready_$i)
begin
$$fdisplay(stderr, "MC$i: w data=%x", w_data_$i);
end
if (r_valid_$i && r_ready_$i)
begin
$$fdisplay(stderr, "MC$i: r data=%x", r_data_$i);
end
end
end
""" } mkString
val f = createOutputFile(s"$topModuleName.$configClassName.tb.vfrag")
f.write(defs + nasti_defs + delays + nasti_delays + instantiation + ticks)
f.close
}
}

3
src/main/scala/Testing.scala
View File

@ -152,6 +152,9 @@ object TestGenerator extends App with FileSystemUtilities {
//Driver.elaborate(gen, configName = configClassName)
TestGeneration.generateMakefrag(topModuleName, configClassName)
TestBenchGeneration.generateVerilogFragement(
topModuleName, configClassName,
paramsFromConfig(NMemoryChannels))
val pdFile = createOutputFile(s"$topModuleName.$configClassName.prm")
pdFile.write(ParameterDump.getDump)