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coreplex: allow MMIO to be misaligned (#1103)

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Wesley W. Terpstra 2017-11-10 15:12:28 -08:00 committed by GitHub
parent a061b16ee3
commit 0cfa801bfc
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1 changed files with 2 additions and 2 deletions
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4
src/main/scala/coreplex/Ports.scala
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@ -86,7 +86,7 @@ trait HasMasterAXI4MMIOPort extends HasSystemBus {
private val device = new SimpleBus("mmio", Nil)
val mmio_axi4 = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(params.base, params.size-1)),
address = AddressSet.misaligned(params.base, params.size),
resources = device.ranges,
executable = params.executable,
supportsWrite = TransferSizes(1, params.maxXferBytes),
@ -165,7 +165,7 @@ trait HasMasterTLMMIOPort extends HasSystemBus {
private val device = new SimpleBus("mmio", Nil)
val mmio_tl = TLManagerNode(Seq(TLManagerPortParameters(
managers = Seq(TLManagerParameters(
address = List(AddressSet(params.base, params.size-1)),
address = AddressSet.misaligned(params.base, params.size),
resources = device.ranges,
executable = params.executable,
supportsGet = TransferSizes(1, sbus.blockBytes),