riscv/rocket-chip
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regressions: test scratchpad

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This commit is contained in:
Wesley W. Terpstra
2016-10-27 22:27:43 -07:00
parent d2e9fa8ec6
commit 0cc00e7616
5 changed files with 21 additions and 12 deletions
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4
src/main/scala/uncore/axi4/Fragmenter.scala
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@ -10,7 +10,7 @@ import scala.math.{min,max}
import uncore.tilelink2.{leftOR, rightOR, UIntToOH1, OH1ToOH}
// lite: masters all use only one ID => reads will not be interleaved
class AXI4Fragmenter(lite: Boolean = false, maxInFlight: Int = 32, combinational: Boolean = true) extends LazyModule
class AXI4Fragmenter(lite: Boolean = false, maxInFlight: => Int = 32, combinational: Boolean = true) extends LazyModule
{
val maxBeats = 1 << AXI4Parameters.lenBits
def expandTransfer(x: TransferSizes, beatBytes: Int, alignment: BigInt) =
@ -287,7 +287,7 @@ class AXI4FragmenterSideband(maxInFlight: Int, flow: Boolean = false) extends Mo
object AXI4Fragmenter
{
// applied to the AXI4 source node; y.node := AXI4Fragmenter()(x.node)
def apply(lite: Boolean = false, maxInFlight: Int = 32, combinational: Boolean = true)(x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = {
def apply(lite: Boolean = false, maxInFlight: => Int = 32, combinational: Boolean = true)(x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = {
val fragmenter = LazyModule(new AXI4Fragmenter(lite, maxInFlight, combinational))
fragmenter.node := x
fragmenter.node

10
src/main/scala/uncore/devices/Plic.scala
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@ -67,18 +67,18 @@ case class PLICConfig(nHartsIn: Int, supervisor: Boolean, nDevices: Int, nPriori
require(nPriorities >= 0 && nPriorities <= nDevices)
}
trait HasPLICParamters {
trait HasPLICParameters {
val params: (() => PLICConfig, Parameters)
val cfg = params._1 ()
implicit val p = params._2
}
trait PLICBundle extends Bundle with HasPLICParamters {
trait PLICBundle extends Bundle with HasPLICParameters {
val devices = Vec(cfg.nDevices, new GatewayPLICIO).flip
val harts = Vec(cfg.nHarts, Bool()).asOutput
}
trait PLICModule extends Module with HasRegMap with HasPLICParamters {
trait PLICModule extends Module with HasRegMap with HasPLICParameters {
val io: PLICBundle
val priority =
@ -118,7 +118,7 @@ trait PLICModule extends Module with HasRegMap with HasPLICParamters {
}
def priorityRegField(x: UInt) = if (cfg.nPriorities > 0) RegField(32, x) else RegField.r(32, x)
val piorityRegFields = Seq(PLICConsts.priorityBase -> priority.map(p => priorityRegField(p)))
val priorityRegFields = Seq(PLICConsts.priorityBase -> priority.map(p => priorityRegField(p)))
val pendingRegFields = Seq(PLICConsts.pendingBase -> pending .map(b => RegField.r(1, b)))
val enableRegFields = enables.zipWithIndex.map { case (e, i) =>
@ -146,7 +146,7 @@ trait PLICModule extends Module with HasRegMap with HasPLICParamters {
)
}
regmap((piorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*)
regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*)
priority(0) := 0
pending(0) := false