From 0cc00e7616e030cf58c896f2786884521ec1ec08 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 27 Oct 2016 22:27:43 -0700 Subject: [PATCH] regressions: test scratchpad --- src/main/scala/groundtest/Configs.scala | 2 +- src/main/scala/rocket/dcache.scala | 11 ++++++++++- src/main/scala/rocket/tile.scala | 6 +++--- src/main/scala/uncore/axi4/Fragmenter.scala | 4 ++-- src/main/scala/uncore/devices/Plic.scala | 10 +++++----- 5 files changed, 21 insertions(+), 12 deletions(-) diff --git a/src/main/scala/groundtest/Configs.scala b/src/main/scala/groundtest/Configs.scala index 64ff77eb..5503e5a4 100644 --- a/src/main/scala/groundtest/Configs.scala +++ b/src/main/scala/groundtest/Configs.scala @@ -114,7 +114,7 @@ class WithGroundTest extends Config( class WithComparator extends Config( (pname, site, here) => pname match { case GroundTestKey => Seq.fill(site(NTiles)) { - GroundTestTileSettings(uncached = site(ComparatorKey).targets.size) + GroundTestTileSettings(uncached = 2) } case BuildGroundTest => (p: Parameters) => Module(new ComparatorCore()(p)) diff --git a/src/main/scala/rocket/dcache.scala b/src/main/scala/rocket/dcache.scala index 4fccc725..bef9e6d4 100644 --- a/src/main/scala/rocket/dcache.scala +++ b/src/main/scala/rocket/dcache.scala @@ -501,15 +501,19 @@ class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule with Ha val beatBytes = p(XLen)/8 val node = TLManagerNode(TLManagerPortParameters( Seq(TLManagerParameters( - address = List(AddressSet(0x80000000L, p(DataScratchpadSize))), + address = List(AddressSet(0x80000000L, BigInt(p(DataScratchpadSize)-1))), regionType = RegionType.UNCACHED, executable = true, supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), + supportsGet = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests handled in FIFO order beatBytes = beatBytes, minLatency = 1)) + // Make sure this ends up with the same name as before + override def name = "dmem0" + lazy val module = new LazyModuleImp(this) { val io = new Bundle { val tl_in = node.bundleIn @@ -566,5 +570,10 @@ class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule with Ha tl_in.d.bits := Mux(isRead, edge.AccessAck(acq, UInt(0), alignedGrantData), edge.AccessAck(acq, UInt(0))) + + // Tie off unused channels + tl_in.b.valid := Bool(false) + tl_in.c.ready := Bool(true) + tl_in.e.ready := Bool(true) } } diff --git a/src/main/scala/rocket/tile.scala b/src/main/scala/rocket/tile.scala index c71848bb..b0391472 100644 --- a/src/main/scala/rocket/tile.scala +++ b/src/main/scala/rocket/tile.scala @@ -54,14 +54,14 @@ abstract class LazyTile(implicit p: Parameters) extends LazyModule { xLen = p(XLen)) val module: TileImp - val slave: Option[TLOutputNode] + val slave: Option[TLInputNode] } class RocketTile(implicit p: Parameters) extends LazyTile { - val slave = if (p(DataScratchpadSize) == 0) None else Some(TLOutputNode()) + val slave = if (p(DataScratchpadSize) == 0) None else Some(TLInputNode()) val scratch = if (p(DataScratchpadSize) == 0) None else Some(LazyModule(new ScratchpadSlavePort()(dcacheParams))) - (slave zip scratch) foreach { case (node, lm) => node := TLFragmenter(p(XLen)/8, p(RowBits)/8)(lm.node) } + (slave zip scratch) foreach { case (node, lm) => lm.node := TLFragmenter(p(XLen)/8, 256)(node) } lazy val module = new TileImp(this) { val io = new TileIO(bc, slave) diff --git a/src/main/scala/uncore/axi4/Fragmenter.scala b/src/main/scala/uncore/axi4/Fragmenter.scala index 939555cb..e933270f 100644 --- a/src/main/scala/uncore/axi4/Fragmenter.scala +++ b/src/main/scala/uncore/axi4/Fragmenter.scala @@ -10,7 +10,7 @@ import scala.math.{min,max} import uncore.tilelink2.{leftOR, rightOR, UIntToOH1, OH1ToOH} // lite: masters all use only one ID => reads will not be interleaved -class AXI4Fragmenter(lite: Boolean = false, maxInFlight: Int = 32, combinational: Boolean = true) extends LazyModule +class AXI4Fragmenter(lite: Boolean = false, maxInFlight: => Int = 32, combinational: Boolean = true) extends LazyModule { val maxBeats = 1 << AXI4Parameters.lenBits def expandTransfer(x: TransferSizes, beatBytes: Int, alignment: BigInt) = @@ -287,7 +287,7 @@ class AXI4FragmenterSideband(maxInFlight: Int, flow: Boolean = false) extends Mo object AXI4Fragmenter { // applied to the AXI4 source node; y.node := AXI4Fragmenter()(x.node) - def apply(lite: Boolean = false, maxInFlight: Int = 32, combinational: Boolean = true)(x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = { + def apply(lite: Boolean = false, maxInFlight: => Int = 32, combinational: Boolean = true)(x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = { val fragmenter = LazyModule(new AXI4Fragmenter(lite, maxInFlight, combinational)) fragmenter.node := x fragmenter.node diff --git a/src/main/scala/uncore/devices/Plic.scala b/src/main/scala/uncore/devices/Plic.scala index 33c7a526..dec058b0 100644 --- a/src/main/scala/uncore/devices/Plic.scala +++ b/src/main/scala/uncore/devices/Plic.scala @@ -67,18 +67,18 @@ case class PLICConfig(nHartsIn: Int, supervisor: Boolean, nDevices: Int, nPriori require(nPriorities >= 0 && nPriorities <= nDevices) } -trait HasPLICParamters { +trait HasPLICParameters { val params: (() => PLICConfig, Parameters) val cfg = params._1 () implicit val p = params._2 } -trait PLICBundle extends Bundle with HasPLICParamters { +trait PLICBundle extends Bundle with HasPLICParameters { val devices = Vec(cfg.nDevices, new GatewayPLICIO).flip val harts = Vec(cfg.nHarts, Bool()).asOutput } -trait PLICModule extends Module with HasRegMap with HasPLICParamters { +trait PLICModule extends Module with HasRegMap with HasPLICParameters { val io: PLICBundle val priority = @@ -118,7 +118,7 @@ trait PLICModule extends Module with HasRegMap with HasPLICParamters { } def priorityRegField(x: UInt) = if (cfg.nPriorities > 0) RegField(32, x) else RegField.r(32, x) - val piorityRegFields = Seq(PLICConsts.priorityBase -> priority.map(p => priorityRegField(p))) + val priorityRegFields = Seq(PLICConsts.priorityBase -> priority.map(p => priorityRegField(p))) val pendingRegFields = Seq(PLICConsts.pendingBase -> pending .map(b => RegField.r(1, b))) val enableRegFields = enables.zipWithIndex.map { case (e, i) => @@ -146,7 +146,7 @@ trait PLICModule extends Module with HasRegMap with HasPLICParamters { ) } - regmap((piorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*) + regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*) priority(0) := 0 pending(0) := false