riscv/rocket-chip
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regressions: test scratchpad

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This commit is contained in:
Wesley W. Terpstra
2016-10-27 22:27:43 -07:00
parent d2e9fa8ec6
commit 0cc00e7616
5 changed files with 21 additions and 12 deletions
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11
src/main/scala/rocket/dcache.scala
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@ -501,15 +501,19 @@ class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule with Ha
val beatBytes = p(XLen)/8
val node = TLManagerNode(TLManagerPortParameters(
Seq(TLManagerParameters(
address = List(AddressSet(0x80000000L, p(DataScratchpadSize))),
address = List(AddressSet(0x80000000L, BigInt(p(DataScratchpadSize)-1))),
regionType = RegionType.UNCACHED,
executable = true,
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
supportsGet = TransferSizes(1, beatBytes),
fifoId = Some(0))), // requests handled in FIFO order
beatBytes = beatBytes,
minLatency = 1))
// Make sure this ends up with the same name as before
override def name = "dmem0"
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val tl_in = node.bundleIn
@ -566,5 +570,10 @@ class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule with Ha
tl_in.d.bits := Mux(isRead,
edge.AccessAck(acq, UInt(0), alignedGrantData),
edge.AccessAck(acq, UInt(0)))
// Tie off unused channels
tl_in.b.valid := Bool(false)
tl_in.c.ready := Bool(true)
tl_in.e.ready := Bool(true)
}
}