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TLDelayer: insert noise on invalid cycles

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This commit is contained in:
Wesley W. Terpstra 2017-03-10 16:48:57 -08:00
parent 1c6dde8c15
commit 0c7fb87390
1 changed files with 47 additions and 6 deletions
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53
src/main/scala/uncore/tilelink2/Delayer.scala
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@ -19,19 +19,60 @@ class TLDelayer(q: Double)(implicit p: Parameters) extends LazyModule
val out = node.bundleOut val out = node.bundleOut
} }
def feed[T <: Data](sink: DecoupledIO[T], source: DecoupledIO[T]) { def feed[T <: Data](sink: DecoupledIO[T], source: DecoupledIO[T], noise: T) {
val allow = UInt((q * 65535.0).toInt) <= LFSR16(source.valid) val allow = UInt((q * 65535.0).toInt) <= LFSR16(source.valid)
sink.valid := source.valid && allow sink.valid := source.valid && allow
source.ready := sink.ready && allow source.ready := sink.ready && allow
sink.bits := source.bits sink.bits := source.bits
when (!sink.valid) { sink.bits := noise }
} }
(io.in zip io.out) foreach { case (in, out) => (io.in zip io.out) foreach { case (in, out) =>
feed(out.a, in.a) val anoise = Wire(in.a.bits)
feed(out.c, in.c) anoise.opcode := LFSRNoiseMaker(3)
feed(out.e, in.e) anoise.param := LFSRNoiseMaker(3)
feed(in.b, out.b) anoise.size := LFSRNoiseMaker(anoise.params.sizeBits)
feed(in.d, out.d) anoise.source := LFSRNoiseMaker(anoise.params.sourceBits)
anoise.address := LFSRNoiseMaker(anoise.params.addressBits)
anoise.mask := LFSRNoiseMaker(anoise.params.dataBits/8)
anoise.data := LFSRNoiseMaker(anoise.params.dataBits)
val bnoise = Wire(out.b.bits)
bnoise.opcode := LFSRNoiseMaker(3)
bnoise.param := LFSRNoiseMaker(3)
bnoise.size := LFSRNoiseMaker(bnoise.params.sizeBits)
bnoise.source := LFSRNoiseMaker(bnoise.params.sourceBits)
bnoise.address := LFSRNoiseMaker(bnoise.params.addressBits)
bnoise.mask := LFSRNoiseMaker(bnoise.params.dataBits/8)
bnoise.data := LFSRNoiseMaker(bnoise.params.dataBits)
val cnoise = Wire(in.c.bits)
cnoise.opcode := LFSRNoiseMaker(3)
cnoise.param := LFSRNoiseMaker(3)
cnoise.size := LFSRNoiseMaker(cnoise.params.sizeBits)
cnoise.source := LFSRNoiseMaker(cnoise.params.sourceBits)
cnoise.address := LFSRNoiseMaker(cnoise.params.addressBits)
cnoise.data := LFSRNoiseMaker(cnoise.params.dataBits)
cnoise.error := LFSRNoiseMaker(1)(0)
val dnoise = Wire(out.d.bits)
dnoise.opcode := LFSRNoiseMaker(3)
dnoise.param := LFSRNoiseMaker(3)
dnoise.size := LFSRNoiseMaker(dnoise.params.sizeBits)
dnoise.source := LFSRNoiseMaker(dnoise.params.sourceBits)
dnoise.sink := LFSRNoiseMaker(dnoise.params.sinkBits)
dnoise.addr_lo := LFSRNoiseMaker(dnoise.params.addrLoBits)
dnoise.data := LFSRNoiseMaker(dnoise.params.dataBits)
dnoise.error := LFSRNoiseMaker(1)(0)
val enoise = Wire(in.e.bits)
enoise.sink := LFSRNoiseMaker(enoise.params.sinkBits)
feed(out.a, in.a, anoise)
feed(out.c, in.c, cnoise)
feed(out.e, in.e, enoise)
feed(in.b, out.b, bnoise)
feed(in.d, out.d, dnoise)
} }
} }
} }