From 0c7fb8739062cb663cdae619d56484cf5d88aac3 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Fri, 10 Mar 2017 16:48:57 -0800
Subject: [PATCH] TLDelayer: insert noise on invalid cycles

---
 src/main/scala/uncore/tilelink2/Delayer.scala | 53 ++++++++++++++++---
 1 file changed, 47 insertions(+), 6 deletions(-)

diff --git a/src/main/scala/uncore/tilelink2/Delayer.scala b/src/main/scala/uncore/tilelink2/Delayer.scala
index 364d8320..06c1be76 100644
--- a/src/main/scala/uncore/tilelink2/Delayer.scala
+++ b/src/main/scala/uncore/tilelink2/Delayer.scala
@@ -19,19 +19,60 @@ class TLDelayer(q: Double)(implicit p: Parameters) extends LazyModule
       val out = node.bundleOut
     }
 
-    def feed[T <: Data](sink: DecoupledIO[T], source: DecoupledIO[T]) {
+    def feed[T <: Data](sink: DecoupledIO[T], source: DecoupledIO[T], noise: T) {
       val allow = UInt((q * 65535.0).toInt) <= LFSR16(source.valid)
       sink.valid := source.valid && allow
       source.ready := sink.ready && allow
       sink.bits := source.bits
+      when (!sink.valid) { sink.bits := noise }
     }
 
     (io.in zip io.out) foreach { case (in, out) =>
-      feed(out.a, in.a)
-      feed(out.c, in.c)
-      feed(out.e, in.e)
-      feed(in.b, out.b)
-      feed(in.d, out.d)
+      val anoise = Wire(in.a.bits)
+      anoise.opcode  := LFSRNoiseMaker(3)
+      anoise.param   := LFSRNoiseMaker(3)
+      anoise.size    := LFSRNoiseMaker(anoise.params.sizeBits)
+      anoise.source  := LFSRNoiseMaker(anoise.params.sourceBits)
+      anoise.address := LFSRNoiseMaker(anoise.params.addressBits)
+      anoise.mask    := LFSRNoiseMaker(anoise.params.dataBits/8)
+      anoise.data    := LFSRNoiseMaker(anoise.params.dataBits)
+
+      val bnoise = Wire(out.b.bits)
+      bnoise.opcode  := LFSRNoiseMaker(3)
+      bnoise.param   := LFSRNoiseMaker(3)
+      bnoise.size    := LFSRNoiseMaker(bnoise.params.sizeBits)
+      bnoise.source  := LFSRNoiseMaker(bnoise.params.sourceBits)
+      bnoise.address := LFSRNoiseMaker(bnoise.params.addressBits)
+      bnoise.mask    := LFSRNoiseMaker(bnoise.params.dataBits/8)
+      bnoise.data    := LFSRNoiseMaker(bnoise.params.dataBits)
+
+      val cnoise = Wire(in.c.bits)
+      cnoise.opcode  := LFSRNoiseMaker(3)
+      cnoise.param   := LFSRNoiseMaker(3)
+      cnoise.size    := LFSRNoiseMaker(cnoise.params.sizeBits)
+      cnoise.source  := LFSRNoiseMaker(cnoise.params.sourceBits)
+      cnoise.address := LFSRNoiseMaker(cnoise.params.addressBits)
+      cnoise.data    := LFSRNoiseMaker(cnoise.params.dataBits)
+      cnoise.error   := LFSRNoiseMaker(1)(0)
+
+      val dnoise = Wire(out.d.bits)
+      dnoise.opcode  := LFSRNoiseMaker(3)
+      dnoise.param   := LFSRNoiseMaker(3)
+      dnoise.size    := LFSRNoiseMaker(dnoise.params.sizeBits)
+      dnoise.source  := LFSRNoiseMaker(dnoise.params.sourceBits)
+      dnoise.sink    := LFSRNoiseMaker(dnoise.params.sinkBits)
+      dnoise.addr_lo := LFSRNoiseMaker(dnoise.params.addrLoBits)
+      dnoise.data    := LFSRNoiseMaker(dnoise.params.dataBits)
+      dnoise.error   := LFSRNoiseMaker(1)(0)
+
+      val enoise = Wire(in.e.bits)
+      enoise.sink := LFSRNoiseMaker(enoise.params.sinkBits)
+
+      feed(out.a, in.a, anoise)
+      feed(out.c, in.c, cnoise)
+      feed(out.e, in.e, enoise)
+      feed(in.b, out.b, bnoise)
+      feed(in.d, out.d, dnoise)
     }
   }
 }