riscv/rocket-chip
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cleanup of conflicts; allocation bugfix

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This commit is contained in:
Henry Cook 2015-02-06 13:20:44 -08:00
parent 7b86ea17cf
commit 0c66e70f14
4 changed files with 13 additions and 13 deletions
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13
uncore/src/main/scala/cache.scala
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@ -397,7 +397,7 @@ class TSHRFile(bankId: Int, innerId: String, outerId: String) extends L2HellaCac
acquireList.zip(alloc_arb.io.in).zipWithIndex.map { case((acq, arb), i) => acquireList.zip(alloc_arb.io.in).zipWithIndex.map { case((acq, arb), i) =>
arb.valid := acq.ready arb.valid := acq.ready
acq.bits := acquire.bits acq.bits := acquire.bits
acq.valid := acquire.valid && (acquire_idx === UInt(i)) acq.valid := arb.ready && (acquire_idx === UInt(i))
} }
val block_acquires = trackerList.map(_.io.has_acquire_conflict).reduce(_||_) val block_acquires = trackerList.map(_.io.has_acquire_conflict).reduce(_||_)
acquire.ready := acquireList.map(_.ready).reduce(_||_) && !block_acquires acquire.ready := acquireList.map(_.ready).reduce(_||_) && !block_acquires
@ -475,7 +475,6 @@ class L2WritebackUnit(trackerId: Int, bankId: Int, innerId: String, outerId: Str
val cacq = io.inner.acquire.bits val cacq = io.inner.acquire.bits
val crel = io.inner.release.bits val crel = io.inner.release.bits
val cgnt = io.inner.grant.bits val cgnt = io.inner.grant.bits
val c_ack = io.inner.finish.bits
val mgnt = io.outer.grant.bits val mgnt = io.outer.grant.bits
val s_idle :: s_probe :: s_data_read :: s_data_resp :: s_outer_write :: Nil = Enum(UInt(), 5) val s_idle :: s_probe :: s_data_read :: s_data_resp :: s_outer_write :: Nil = Enum(UInt(), 5)
@ -498,7 +497,7 @@ class L2WritebackUnit(trackerId: Int, bankId: Int, innerId: String, outerId: Str
val resp_data_done = connectIncomingDataBeatCounter(io.data.resp) val resp_data_done = connectIncomingDataBeatCounter(io.data.resp)
io.has_release_match := !crel.payload.isVoluntary() && io.has_release_match := !crel.payload.isVoluntary() &&
co.isCoherenceConflict(xact_addr_block, crel.payload.addr_block) && crel.payload.conflicts(xact_addr_block) &&
(state === s_probe) (state === s_probe)
val next_coh_on_rel = co.managerMetadataOnRelease(crel.payload, xact_coh, crel.header.src) val next_coh_on_rel = co.managerMetadataOnRelease(crel.payload, xact_coh, crel.header.src)
@ -824,12 +823,12 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
} }
//TODO: Allow hit under miss for stores //TODO: Allow hit under miss for stores
io.has_acquire_conflict := (co.isCoherenceConflict(xact.addr_block, cacq.payload.addr_block) || val in_same_set = xact.addr_block(idxMSB,idxLSB) ===
xact.addr_block(idxMSB,idxLSB) === cacq.payload.addr_block(idxMSB,idxLSB)) && cacq.payload.addr_block(idxMSB,idxLSB)
io.has_acquire_conflict := (xact.conflicts(cacq.payload) || in_same_set) &&
(state != s_idle) && (state != s_idle) &&
!collect_cacq_data !collect_cacq_data
io.has_acquire_match := xact.hasMultibeatData() && io.has_acquire_match := xact.conflicts(cacq.payload) &&
(xact.addr_block === cacq.payload.addr_block) &&
collect_cacq_data collect_cacq_data
io.has_release_match := !crel.payload.isVoluntary() && io.has_release_match := !crel.payload.isVoluntary() &&
(xact.addr_block === crel.payload.addr_block) && (xact.addr_block === crel.payload.addr_block) &&

2
uncore/src/main/scala/coherence.scala
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@ -135,8 +135,6 @@ abstract class CoherencePolicy(val dir: DirectoryRepresentation) {
def requiresProbes(acq: Acquire, meta: ManagerMetadata): Bool def requiresProbes(acq: Acquire, meta: ManagerMetadata): Bool
def requiresProbes(cmd: UInt, meta: ManagerMetadata): Bool def requiresProbes(cmd: UInt, meta: ManagerMetadata): Bool
def requiresProbesOnVoluntaryWriteback(meta: ManagerMetadata): Bool = requiresProbes(M_FLUSH, meta) def requiresProbesOnVoluntaryWriteback(meta: ManagerMetadata): Bool = requiresProbes(M_FLUSH, meta)
def isCoherenceConflict(addr1: UInt, addr2: UInt): Bool
} }
class MICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) { class MICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {

3
uncore/src/main/scala/tilelink.scala
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@ -49,6 +49,9 @@ trait ClientToClientChannel extends TileLinkChannel // Unused for now
// //
trait HasCacheBlockAddress extends TLBundle { trait HasCacheBlockAddress extends TLBundle {
val addr_block = UInt(width = tlBlockAddrBits) val addr_block = UInt(width = tlBlockAddrBits)
def conflicts[T <: HasCacheBlockAddress](that: T) = this.addr_block === that.addr_block
def conflicts[T <: HasCacheBlockAddress](addr: UInt) = this.addr_block === addr
} }
trait HasTileLinkBeatId extends TLBundle { trait HasTileLinkBeatId extends TLBundle {

8
uncore/src/main/scala/uncore.scala
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@ -300,10 +300,10 @@ class AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: Stri
val myflag = Mux(probe_self, Bits(0), UIntToOH(cacq.header.src(log2Up(nClients)-1,0))) val myflag = Mux(probe_self, Bits(0), UIntToOH(cacq.header.src(log2Up(nClients)-1,0)))
probe_initial_flags := ~(io.tile_incoherent | myflag) probe_initial_flags := ~(io.tile_incoherent | myflag)
io.has_acquire_conflict := co.isCoherenceConflict(xact_addr_block, cacq.payload.addr_block) && io.has_acquire_conflict := xact.conflicts(cacq.payload) &&
(state != s_idle) && !collect_inner_data &&
!collect_inner_data (state != s_idle)
io.has_release_match := co.isCoherenceConflict(xact_addr_block, crel.payload.addr_block) && io.has_release_match := xact.conflicts(crel.payload) &&
!crel.payload.isVoluntary() && !crel.payload.isVoluntary() &&
(state != s_idle) (state != s_idle)