From 0c66e70f147273726f3b823249a7f20a520029af Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Fri, 6 Feb 2015 13:20:44 -0800 Subject: [PATCH] cleanup of conflicts; allocation bugfix --- uncore/src/main/scala/cache.scala | 13 ++++++------- uncore/src/main/scala/coherence.scala | 2 -- uncore/src/main/scala/tilelink.scala | 3 +++ uncore/src/main/scala/uncore.scala | 8 ++++---- 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/uncore/src/main/scala/cache.scala b/uncore/src/main/scala/cache.scala index a033be2f..859e0bc3 100644 --- a/uncore/src/main/scala/cache.scala +++ b/uncore/src/main/scala/cache.scala @@ -397,7 +397,7 @@ class TSHRFile(bankId: Int, innerId: String, outerId: String) extends L2HellaCac acquireList.zip(alloc_arb.io.in).zipWithIndex.map { case((acq, arb), i) => arb.valid := acq.ready acq.bits := acquire.bits - acq.valid := acquire.valid && (acquire_idx === UInt(i)) + acq.valid := arb.ready && (acquire_idx === UInt(i)) } val block_acquires = trackerList.map(_.io.has_acquire_conflict).reduce(_||_) acquire.ready := acquireList.map(_.ready).reduce(_||_) && !block_acquires @@ -475,7 +475,6 @@ class L2WritebackUnit(trackerId: Int, bankId: Int, innerId: String, outerId: Str val cacq = io.inner.acquire.bits val crel = io.inner.release.bits val cgnt = io.inner.grant.bits - val c_ack = io.inner.finish.bits val mgnt = io.outer.grant.bits val s_idle :: s_probe :: s_data_read :: s_data_resp :: s_outer_write :: Nil = Enum(UInt(), 5) @@ -498,7 +497,7 @@ class L2WritebackUnit(trackerId: Int, bankId: Int, innerId: String, outerId: Str val resp_data_done = connectIncomingDataBeatCounter(io.data.resp) io.has_release_match := !crel.payload.isVoluntary() && - co.isCoherenceConflict(xact_addr_block, crel.payload.addr_block) && + crel.payload.conflicts(xact_addr_block) && (state === s_probe) val next_coh_on_rel = co.managerMetadataOnRelease(crel.payload, xact_coh, crel.header.src) @@ -824,12 +823,12 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St } //TODO: Allow hit under miss for stores - io.has_acquire_conflict := (co.isCoherenceConflict(xact.addr_block, cacq.payload.addr_block) || - xact.addr_block(idxMSB,idxLSB) === cacq.payload.addr_block(idxMSB,idxLSB)) && + val in_same_set = xact.addr_block(idxMSB,idxLSB) === + cacq.payload.addr_block(idxMSB,idxLSB) + io.has_acquire_conflict := (xact.conflicts(cacq.payload) || in_same_set) && (state != s_idle) && !collect_cacq_data - io.has_acquire_match := xact.hasMultibeatData() && - (xact.addr_block === cacq.payload.addr_block) && + io.has_acquire_match := xact.conflicts(cacq.payload) && collect_cacq_data io.has_release_match := !crel.payload.isVoluntary() && (xact.addr_block === crel.payload.addr_block) && diff --git a/uncore/src/main/scala/coherence.scala b/uncore/src/main/scala/coherence.scala index 201e67ab..82f72dea 100644 --- a/uncore/src/main/scala/coherence.scala +++ b/uncore/src/main/scala/coherence.scala @@ -135,8 +135,6 @@ abstract class CoherencePolicy(val dir: DirectoryRepresentation) { def requiresProbes(acq: Acquire, meta: ManagerMetadata): Bool def requiresProbes(cmd: UInt, meta: ManagerMetadata): Bool def requiresProbesOnVoluntaryWriteback(meta: ManagerMetadata): Bool = requiresProbes(M_FLUSH, meta) - - def isCoherenceConflict(addr1: UInt, addr2: UInt): Bool } class MICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) { diff --git a/uncore/src/main/scala/tilelink.scala b/uncore/src/main/scala/tilelink.scala index 3fc0e4e7..afbf4dc0 100644 --- a/uncore/src/main/scala/tilelink.scala +++ b/uncore/src/main/scala/tilelink.scala @@ -49,6 +49,9 @@ trait ClientToClientChannel extends TileLinkChannel // Unused for now // trait HasCacheBlockAddress extends TLBundle { val addr_block = UInt(width = tlBlockAddrBits) + + def conflicts[T <: HasCacheBlockAddress](that: T) = this.addr_block === that.addr_block + def conflicts[T <: HasCacheBlockAddress](addr: UInt) = this.addr_block === addr } trait HasTileLinkBeatId extends TLBundle { diff --git a/uncore/src/main/scala/uncore.scala b/uncore/src/main/scala/uncore.scala index cc4755f0..1230771c 100644 --- a/uncore/src/main/scala/uncore.scala +++ b/uncore/src/main/scala/uncore.scala @@ -300,10 +300,10 @@ class AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: Stri val myflag = Mux(probe_self, Bits(0), UIntToOH(cacq.header.src(log2Up(nClients)-1,0))) probe_initial_flags := ~(io.tile_incoherent | myflag) - io.has_acquire_conflict := co.isCoherenceConflict(xact_addr_block, cacq.payload.addr_block) && - (state != s_idle) && - !collect_inner_data - io.has_release_match := co.isCoherenceConflict(xact_addr_block, crel.payload.addr_block) && + io.has_acquire_conflict := xact.conflicts(cacq.payload) && + !collect_inner_data && + (state != s_idle) + io.has_release_match := xact.conflicts(crel.payload) && !crel.payload.isVoluntary() && (state != s_idle)