riscv/rocket-chip
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cleanup of conflicts; allocation bugfix

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This commit is contained in:
Henry Cook
2015-02-06 13:20:44 -08:00
parent 7b86ea17cf
commit 0c66e70f14
4 changed files with 13 additions and 13 deletions
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8
uncore/src/main/scala/uncore.scala
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@ -300,10 +300,10 @@ class AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: Stri
val myflag = Mux(probe_self, Bits(0), UIntToOH(cacq.header.src(log2Up(nClients)-1,0)))
probe_initial_flags := ~(io.tile_incoherent | myflag)
io.has_acquire_conflict := co.isCoherenceConflict(xact_addr_block, cacq.payload.addr_block) &&
(state != s_idle) &&
!collect_inner_data
io.has_release_match := co.isCoherenceConflict(xact_addr_block, crel.payload.addr_block) &&
io.has_acquire_conflict := xact.conflicts(cacq.payload) &&
!collect_inner_data &&
(state != s_idle)
io.has_release_match := xact.conflicts(crel.payload) &&
!crel.payload.isVoluntary() &&
(state != s_idle)