riscv/rocket-chip
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make AtosSerializedIO clock divisible

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This commit is contained in:
Howard Mao 2016-02-24 23:10:06 -08:00
parent 1dc8af894e
commit 0bf8d07aba
1 changed files with 2 additions and 0 deletions
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junctions/src/main/scala/atos.scala
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@ -293,6 +293,8 @@ class AtosManagerConverter(implicit p: Parameters) extends AtosModule()(p) {
class AtosSerializedIO(w: Int)(implicit p: Parameters) extends ParameterizedBundle()(p) { class AtosSerializedIO(w: Int)(implicit p: Parameters) extends ParameterizedBundle()(p) {
val req = Decoupled(Bits(width = w)) val req = Decoupled(Bits(width = w))
val resp = Decoupled(Bits(width = w)).flip val resp = Decoupled(Bits(width = w)).flip
val clk = Bool(OUTPUT)
val clk_edge = Bool(OUTPUT)
override def cloneType = new AtosSerializedIO(w)(p).asInstanceOf[this.type] override def cloneType = new AtosSerializedIO(w)(p).asInstanceOf[this.type]
} }