riscv/rocket-chip
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changed coherence message type names

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This commit is contained in:
Henry Cook
2012-04-03 18:06:02 -07:00
parent ed79ec98f7
commit 0b4937f70f
6 changed files with 91 additions and 108 deletions
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5
rocket/src/main/scala/icache.scala
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@ -27,7 +27,8 @@ class ioRocketICache extends Bundle()
// 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
// parameters :
// lines = # cache lines
class rocketICache(sets: Int, assoc: Int) extends Component {
class rocketICache(sets: Int, assoc: Int) extends Component with FourStateCoherence
{
val io = new ioRocketICache();
val lines = sets * assoc;
@ -135,7 +136,7 @@ class rocketICache(sets: Int, assoc: Int) extends Component {
rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || tag_hit);
io.cpu.resp_data := data_mux.io.out
io.mem.xact_init.valid := (state === s_request) && finish_q.io.enq.ready
io.mem.xact_init.bits.t_type := X_INIT_READ_UNCACHED
io.mem.xact_init.bits.x_type := xactInitReadUncached
io.mem.xact_init.bits.address := r_cpu_miss_addr(tagmsb,indexlsb).toUFix
io.mem.xact_finish <> finish_q.io.deq