diff --git a/rocket/src/main/scala/coherence.scala b/rocket/src/main/scala/coherence.scala
index ee51e469..7af9c903 100644
--- a/rocket/src/main/scala/coherence.scala
+++ b/rocket/src/main/scala/coherence.scala
@@ -4,7 +4,7 @@ import Chisel._
 import Constants._
 
 class TransactionInit extends Bundle {
-  val t_type = Bits(width = X_INIT_TYPE_BITS)
+  val x_type = Bits(width = X_INIT_TYPE_BITS)
   val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
   val address = UFix(width = PADDR_BITS - OFFSET_BITS)
 }
@@ -29,7 +29,7 @@ class ProbeReply extends Bundle {
 class ProbeReplyData extends MemData
 
 class TransactionReply extends MemData {
-  val t_type = Bits(width = X_REP_TYPE_BITS)
+  val x_type = Bits(width = X_REP_TYPE_BITS)
   val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
   val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
   val require_ack = Bool()
@@ -54,13 +54,13 @@ trait CoherencePolicy { }
 
 trait ThreeStateIncoherence extends CoherencePolicy {
   val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() }
-  val X_INIT_READ_SHARED    = UFix(0, 2)
-  val X_INIT_READ_EXCLUSIVE = UFix(1, 2)
-  val X_INIT_WRITE_UNCACHED = UFix(3, 2)
-  val X_REP_READ_SHARED    = UFix(0, X_REP_TYPE_BITS)
-  val X_REP_READ_EXCLUSIVE = UFix(1, X_REP_TYPE_BITS)
-  val X_REP_WRITE_UNCACHED = UFix(3, X_REP_TYPE_BITS)
-  val P_REP_INVALIDATE_ACK  = UFix(3, P_REP_TYPE_BITS)
+  val xactInitReadShared    = UFix(0, 2)
+  val xactInitReadExclusive = UFix(1, 2)
+  val xactInitWriteUncached = UFix(3, 2)
+  val xactReplyReadShared    = UFix(0, X_REP_TYPE_BITS)
+  val xactReplyReadExclusive = UFix(1, X_REP_TYPE_BITS)
+  val xactReplyWriteUncached = UFix(3, X_REP_TYPE_BITS)
+  val probeRepInvalidateAck  = UFix(3, P_REP_TYPE_BITS)
 
   def isHit ( cmd: Bits, state: UFix): Bool = {
     val (read, write) = cpuCmdToRW(cmd)
@@ -84,57 +84,38 @@ trait ThreeStateIncoherence extends CoherencePolicy {
   def newStateOnHit(cmd: Bits, state: UFix): UFix = newState(cmd, state)
   def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
     val (read, write) = cpuCmdToRW(cmd)
-    Mux(write || cmd === M_PFW, X_INIT_READ_EXCLUSIVE, X_INIT_READ_SHARED)
+    Mux(write || cmd === M_PFW, xactInitReadExclusive, xactInitReadShared)
   }
   def getTransactionInitTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: TransactionInit): UFix = {
     val (read, write) = cpuCmdToRW(cmd)
-    Mux(write, X_INIT_READ_EXCLUSIVE, outstanding.t_type)
+    Mux(write, xactInitReadExclusive, outstanding.x_type)
   }
   def needsTransactionOnSecondaryMiss(cmd: Bits, outstanding: TransactionInit): Bool = Bool(false)
   def newStateOnTransactionReply(incoming: TransactionReply, outstanding: TransactionInit): UFix = {
-    Mux(outstanding.t_type === X_INIT_READ_EXCLUSIVE, tileDirty, tileClean)
+    Mux(outstanding.x_type === xactInitReadExclusive, tileDirty, tileClean)
   } 
   def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = state
   def newProbeReply (incoming: ProbeRequest, has_data: Bool): ProbeReply = {
     val reply = Wire() { new ProbeReply() }
-    reply.p_type := P_REP_INVALIDATE_ACK
+    reply.p_type := probeRepInvalidateAck
     reply.global_xact_id := UFix(0)
     reply
   }
   def probeReplyHasData (reply: ProbeReply): Bool = Bool(false)
-  def transactionInitHasData (init: TransactionInit): Bool = (init.t_type === X_INIT_WRITE_UNCACHED)
+  def transactionInitHasData (init: TransactionInit): Bool = (init.x_type === xactInitWriteUncached)
 }
 
 trait FourStateCoherence extends CoherencePolicy {
 
   val tileInvalid :: tileShared :: tileExclusiveClean :: tileExclusiveDirty :: Nil = Enum(4){ UFix() }
   val globalInvalid :: globalShared :: globalExclusiveClean :: Nil = Enum(3){ UFix() }
-  val probeInvalidate :: probeDowngrade :: probeCopy :: Nil = Enum(3){ UFix() }
 
-  val X_INIT_READ_SHARED    = UFix(0, X_INIT_TYPE_BITS)
-  val X_INIT_READ_EXCLUSIVE = UFix(1, X_INIT_TYPE_BITS)
-  val X_INIT_READ_UNCACHED  = UFix(2, X_INIT_TYPE_BITS)
-  val X_INIT_WRITE_UNCACHED = UFix(3, X_INIT_TYPE_BITS)
+  val xactInitReadShared :: xactInitReadExclusive :: xactInitReadUncached :: xactInitWriteUncached :: Nil = Enum(4){ UFix() }
+  val xactReplyReadShared :: xactReplyReadExclusive :: xactReplyReadUncached :: xactReplyWriteUncached :: xactReplyReadExclusiveAck :: Nil = Enum(5){ UFix() } 
+  val probeReqInvalidate :: probeReqDowngrade :: probeReqCopy :: Nil = Enum(3){ UFix() }
+  val probeRepInvalidateData :: probeRepDowngradeData :: probeRepCopyData :: probeRepInvalidateAck :: probeRepDowngradeAck :: probeRepCopyAck :: Nil = Enum(6){ UFix() }
 
-  val X_REP_READ_SHARED    = UFix(0, X_REP_TYPE_BITS)
-  val X_REP_READ_EXCLUSIVE = UFix(1, X_REP_TYPE_BITS)
-  val X_REP_READ_UNCACHED  = UFix(2, X_REP_TYPE_BITS)
-  val X_REP_WRITE_UNCACHED = UFix(3, X_REP_TYPE_BITS)
-  val X_REP_READ_EXCLUSIVE_ACK = UFix(4, X_REP_TYPE_BITS)
-
-  val P_REQ_INVALIDATE = UFix(0, P_REQ_TYPE_BITS)
-  val P_REQ_DOWNGRADE  = UFix(1, P_REQ_TYPE_BITS)
-  val P_REQ_COPY       = UFix(2, P_REQ_TYPE_BITS)
-
-  val P_REP_INVALIDATE_DATA = UFix(0, P_REP_TYPE_BITS)
-  val P_REP_DOWNGRADE_DATA  = UFix(1, P_REP_TYPE_BITS)
-  val P_REP_COPY_DATA       = UFix(2, P_REP_TYPE_BITS)
-  val P_REP_INVALIDATE_ACK  = UFix(3, P_REP_TYPE_BITS)
-  val P_REP_DOWNGRADE_ACK   = UFix(4, P_REP_TYPE_BITS)
-  val P_REP_COPY_ACK        = UFix(5, P_REP_TYPE_BITS)
-
-
-  def isHit ( cmd: Bits, state: UFix): Bool = {
+  def isHit (cmd: Bits, state: UFix): Bool = {
     val (read, write) = cpuCmdToRW(cmd)
     Mux(write, (state === tileExclusiveClean || state === tileExclusiveDirty),
         (state === tileShared || state === tileExclusiveClean || state === tileExclusiveDirty))
@@ -145,8 +126,8 @@ trait FourStateCoherence extends CoherencePolicy {
 
   def needsTransactionOnSecondaryMiss(cmd: Bits, outstanding: TransactionInit): Bool = {
     val (read, write) = cpuCmdToRW(cmd)
-    (read && (outstanding.t_type === X_INIT_READ_UNCACHED || outstanding.t_type === X_INIT_WRITE_UNCACHED)) ||
-      (write && (outstanding.t_type != X_INIT_READ_EXCLUSIVE))
+    (read && (outstanding.x_type === xactInitReadUncached || outstanding.x_type === xactInitWriteUncached)) ||
+      (write && (outstanding.x_type != xactInitReadExclusive))
   }
   def needsTransactionOnCacheControl(cmd: Bits, state: UFix): Bool = {
     MuxLookup(cmd, (state === tileExclusiveDirty), Array(
@@ -171,44 +152,44 @@ trait FourStateCoherence extends CoherencePolicy {
   def newStateOnWriteback() = newStateOnCacheControl(M_INV)
   def newStateOnFlush() = newStateOnCacheControl(M_INV)
   def newStateOnTransactionReply(incoming: TransactionReply, outstanding: TransactionInit): UFix = {
-    MuxLookup(incoming.t_type, tileInvalid, Array(
-      X_REP_READ_SHARED -> tileShared,
-      X_REP_READ_EXCLUSIVE  -> Mux(outstanding.t_type === X_INIT_READ_EXCLUSIVE, tileExclusiveDirty, tileExclusiveClean),
-      X_REP_READ_EXCLUSIVE_ACK -> tileExclusiveDirty, 
-      X_REP_READ_UNCACHED -> tileInvalid,
-      X_REP_WRITE_UNCACHED -> tileInvalid
+    MuxLookup(incoming.x_type, tileInvalid, Array(
+      xactReplyReadShared -> tileShared,
+      xactReplyReadExclusive  -> Mux(outstanding.x_type === xactInitReadExclusive, tileExclusiveDirty, tileExclusiveClean),
+      xactReplyReadExclusiveAck -> tileExclusiveDirty, 
+      xactReplyReadUncached -> tileInvalid,
+      xactReplyWriteUncached -> tileInvalid
     ))
   } 
   def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = {
     MuxLookup(incoming.p_type, state, Array(
-      probeInvalidate -> tileInvalid,
-      probeDowngrade  -> tileShared,
-      probeCopy       -> state
+      probeReqInvalidate -> tileInvalid,
+      probeReqDowngrade  -> tileShared,
+      probeReqCopy       -> state
     ))
   }
 
   def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
     val (read, write) = cpuCmdToRW(cmd)
-    Mux(write || cmd === M_PFW, X_INIT_READ_EXCLUSIVE, X_INIT_READ_SHARED)
+    Mux(write || cmd === M_PFW, xactInitReadExclusive, xactInitReadShared)
   }
   def getTransactionInitTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: TransactionInit): UFix = {
     val (read, write) = cpuCmdToRW(cmd)
-    Mux(write, X_INIT_READ_EXCLUSIVE, outstanding.t_type)
+    Mux(write, xactInitReadExclusive, outstanding.x_type)
   }
-  def getTransactionInitTypeOnCacheControl(cmd: Bits): Bits = X_INIT_WRITE_UNCACHED
+  def getTransactionInitTypeOnCacheControl(cmd: Bits): Bits = xactInitWriteUncached
   def getTransactionInitTypeOnWriteback(): Bits = getTransactionInitTypeOnCacheControl(M_INV)
 
   def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
     val reply = Wire() { new ProbeReply() }
-    val with_data = MuxLookup(incoming.p_type, P_REP_INVALIDATE_DATA, Array(
-      probeInvalidate -> P_REP_INVALIDATE_DATA,
-      probeDowngrade  -> P_REP_DOWNGRADE_DATA,
-      probeCopy       -> P_REP_COPY_DATA
+    val with_data = MuxLookup(incoming.p_type, probeRepInvalidateData, Array(
+      probeReqInvalidate -> probeRepInvalidateData,
+      probeReqDowngrade  -> probeRepDowngradeData,
+      probeReqCopy       -> probeRepCopyData
     ))
-    val without_data = MuxLookup(incoming.p_type, P_REP_INVALIDATE_ACK, Array(
-      probeInvalidate -> P_REP_INVALIDATE_ACK,
-      probeDowngrade  -> P_REP_DOWNGRADE_ACK,
-      probeCopy       -> P_REP_COPY_ACK
+    val without_data = MuxLookup(incoming.p_type, probeRepInvalidateAck, Array(
+      probeReqInvalidate -> probeRepInvalidateAck,
+      probeReqDowngrade  -> probeRepDowngradeAck,
+      probeReqCopy       -> probeRepCopyAck
     ))
     reply.p_type := Mux(needsWriteback(state), with_data, without_data)
     reply.global_xact_id := incoming.global_xact_id
@@ -216,44 +197,44 @@ trait FourStateCoherence extends CoherencePolicy {
   }
 
   def hasData (reply: ProbeReply): Bool = {
-    (reply.p_type === P_REP_INVALIDATE_DATA ||
-     reply.p_type === P_REP_DOWNGRADE_DATA ||
-     reply.p_type === P_REP_COPY_DATA)
+    (reply.p_type === probeRepInvalidateData ||
+     reply.p_type === probeRepDowngradeData ||
+     reply.p_type === probeRepCopyData)
   }
   def hasData (init: TransactionInit): Bool = {
-    (init.t_type === X_INIT_WRITE_UNCACHED)
+    (init.x_type === xactInitWriteUncached)
   }
   def hasData (reply: TransactionReply): Bool = {
-    (reply.t_type != X_REP_WRITE_UNCACHED && reply.t_type != X_REP_READ_EXCLUSIVE_ACK)
+    (reply.x_type != xactReplyWriteUncached && reply.x_type != xactReplyReadExclusiveAck)
   }
 
   def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2)
 
-  def getTransactionReplyType(t_type: UFix, count: UFix): Bits = {
-    MuxLookup(t_type, X_REP_READ_UNCACHED, Array(
-      X_INIT_READ_SHARED    -> Mux(count > UFix(0), X_REP_READ_SHARED, X_REP_READ_EXCLUSIVE),
-      X_INIT_READ_EXCLUSIVE -> X_REP_READ_EXCLUSIVE,
-      X_INIT_READ_UNCACHED  -> X_REP_READ_UNCACHED,
-      X_INIT_WRITE_UNCACHED -> X_REP_WRITE_UNCACHED
+  def getTransactionReplyType(x_type: UFix, count: UFix): Bits = {
+    MuxLookup(x_type, xactReplyReadUncached, Array(
+      xactInitReadShared    -> Mux(count > UFix(0), xactReplyReadShared, xactReplyReadExclusive),
+      xactInitReadExclusive -> xactReplyReadExclusive,
+      xactInitReadUncached  -> xactReplyReadUncached,
+      xactInitWriteUncached -> xactReplyWriteUncached
     ))
   }
 
-  def getProbeRequestType(t_type: UFix, global_state: UFix): UFix = {
-    MuxLookup(t_type, P_REQ_COPY, Array(
-      X_INIT_READ_SHARED -> P_REQ_DOWNGRADE,
-      X_INIT_READ_EXCLUSIVE -> P_REQ_INVALIDATE, 
-      X_INIT_READ_UNCACHED -> P_REQ_COPY, 
-      X_INIT_WRITE_UNCACHED -> P_REQ_INVALIDATE
+  def getProbeRequestType(x_type: UFix, global_state: UFix): UFix = {
+    MuxLookup(x_type, probeReqCopy, Array(
+      xactInitReadShared -> probeReqDowngrade,
+      xactInitReadExclusive -> probeReqInvalidate, 
+      xactInitReadUncached -> probeReqCopy, 
+      xactInitWriteUncached -> probeReqInvalidate
     ))
   }
 
-  def needsMemRead(t_type: UFix, global_state: UFix): Bool = {
-      (t_type != X_INIT_WRITE_UNCACHED)
+  def needsMemRead(x_type: UFix, global_state: UFix): Bool = {
+      (x_type != xactInitWriteUncached)
   }
-  def needsMemWrite(t_type: UFix, global_state: UFix): Bool = {
-      (t_type === X_INIT_WRITE_UNCACHED)
+  def needsMemWrite(x_type: UFix, global_state: UFix): Bool = {
+      (x_type === xactInitWriteUncached)
   }
-  def needsAckReply(t_type: UFix, global_state: UFix): Bool = {
-      (t_type === X_INIT_WRITE_UNCACHED)
+  def needsAckReply(x_type: UFix, global_state: UFix): Bool = {
+      (x_type === xactInitWriteUncached)
   }
 }
diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala
index 253fdf14..0b312136 100644
--- a/rocket/src/main/scala/htif.scala
+++ b/rocket/src/main/scala/htif.scala
@@ -165,7 +165,7 @@ class rocketHTIF(w: Int, ncores: Int) extends Component with FourStateCoherence
     mem_req_data = Cat(packet_ram(idx), mem_req_data)
   }
   io.mem.xact_init.valid := state === state_mem_req
-  io.mem.xact_init.bits.t_type := Mux(cmd === cmd_writemem, X_INIT_WRITE_UNCACHED, X_INIT_READ_UNCACHED)
+  io.mem.xact_init.bits.x_type := Mux(cmd === cmd_writemem, xactInitWriteUncached, xactInitReadUncached)
   io.mem.xact_init.bits.address := addr >> UFix(OFFSET_BITS-3)
   io.mem.xact_init_data.valid:= state === state_mem_wdata
   io.mem.xact_init_data.bits.data := mem_req_data
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index 79ee7a23..08d44ae7 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -27,7 +27,8 @@ class ioRocketICache extends Bundle()
 // 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
 // parameters :
 //    lines = # cache lines
-class rocketICache(sets: Int, assoc: Int) extends Component {
+class rocketICache(sets: Int, assoc: Int) extends Component with FourStateCoherence
+{
   val io = new ioRocketICache();
 
   val lines = sets * assoc;
@@ -135,7 +136,7 @@ class rocketICache(sets: Int, assoc: Int) extends Component {
   rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || tag_hit);
   io.cpu.resp_data := data_mux.io.out
   io.mem.xact_init.valid := (state === s_request) && finish_q.io.enq.ready
-  io.mem.xact_init.bits.t_type := X_INIT_READ_UNCACHED
+  io.mem.xact_init.bits.x_type := xactInitReadUncached
   io.mem.xact_init.bits.address := r_cpu_miss_addr(tagmsb,indexlsb).toUFix
   io.mem.xact_finish <> finish_q.io.deq
 
diff --git a/rocket/src/main/scala/icache_prefetch.scala b/rocket/src/main/scala/icache_prefetch.scala
index 1781175e..9e2b52f5 100644
--- a/rocket/src/main/scala/icache_prefetch.scala
+++ b/rocket/src/main/scala/icache_prefetch.scala
@@ -11,7 +11,8 @@ class ioIPrefetcher extends Bundle() {
   val invalidate = Bool(INPUT)
 }
 
-class rocketIPrefetcher extends Component() {
+class rocketIPrefetcher extends Component with FourStateCoherence
+{
   val io = new ioIPrefetcher();
   val pdq = (new queue(REFILL_CYCLES, flushable = true)) { Bits(width = MEM_DATA_BITS) };
 
@@ -33,7 +34,7 @@ class rocketIPrefetcher extends Component() {
   val finish_q = (new queue(1)) { new TransactionFinish }
   io.mem.xact_abort.ready := Bool(true)
   io.mem.xact_init.valid  := prefetch_miss || (state === s_req_wait) && finish_q.io.enq.ready
-  io.mem.xact_init.bits.t_type := X_INIT_READ_UNCACHED
+  io.mem.xact_init.bits.x_type := xactInitReadUncached
   io.mem.xact_init.bits.tile_xact_id  := Mux(prefetch_miss, UFix(0), UFix(1))
   io.mem.xact_init.bits.address := Mux(prefetch_miss, io.icache.xact_init.bits.address, prefetch_addr);
 
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index aed8fb82..a26f6634 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -188,7 +188,7 @@ class MSHR(id: Int) extends Component with FourStateCoherence {
   val state = Reg(resetVal = s_invalid)
   val flush = Reg { Bool() }
 
-  val xact_type = Reg { UFix() }
+  val xacx_type = Reg { UFix() }
   val line_state = Reg { UFix() }
   val refill_count = Reg { UFix(width = log2up(REFILL_CYCLES)) }
   val req = Reg { new MSHRReq() }
@@ -239,13 +239,13 @@ class MSHR(id: Int) extends Component with FourStateCoherence {
   }
 
   when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req
-    xact_type := getTransactionInitTypeOnSecondaryMiss(req_cmd, newStateOnFlush(), io.mem_req.bits)
+    xacx_type := getTransactionInitTypeOnSecondaryMiss(req_cmd, newStateOnFlush(), io.mem_req.bits)
   }
   when ((state === s_invalid) && io.req_pri_val) {
     flush := req_cmd === M_FLA
     line_state := newStateOnFlush()
     refill_count := UFix(0)
-    xact_type := getTransactionInitTypeOnPrimaryMiss(req_cmd, newStateOnFlush())
+    xacx_type := getTransactionInitTypeOnPrimaryMiss(req_cmd, newStateOnFlush())
     req := io.req_bits
 
     when (io.req_bits.tag_miss) {
@@ -278,7 +278,7 @@ class MSHR(id: Int) extends Component with FourStateCoherence {
   io.probe_refill.ready := (state != s_refill_resp) || !idx_match
 
   io.mem_req.valid := (state === s_refill_req) && !flush
-  io.mem_req.bits.t_type := xact_type
+  io.mem_req.bits.x_type := xacx_type
   io.mem_req.bits.address := Cat(req.tag, req.idx).toUFix
   io.mem_req.bits.tile_xact_id := Bits(id)
   io.mem_finish <> finish_q.io.deq
@@ -469,7 +469,7 @@ class WritebackUnit extends Component with FourStateCoherence{
   io.data_req.bits.data := Bits(0)
 
   io.mem_req.valid := valid && !cmd_sent
-  io.mem_req.bits.t_type := getTransactionInitTypeOnWriteback()
+  io.mem_req.bits.x_type := getTransactionInitTypeOnWriteback()
   io.mem_req.bits.address := Cat(req.tag, req.idx).toUFix
   io.mem_req.bits.tile_xact_id := req.tile_xact_id
   io.mem_req_data.valid := data_req_fired && !is_probe
@@ -894,7 +894,7 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
   data_arb.io.in(0).bits.wmask := ~UFix(0, MEM_DATA_BITS/8)
   data_arb.io.in(0).bits.data := io.mem.xact_rep.bits.data
   data_arb.io.in(0).bits.way_en := mshr.io.mem_resp_way_oh
-  data_arb.io.in(0).valid := io.mem.xact_rep.valid && (io.mem.xact_rep.bits.t_type === X_REP_READ_SHARED || io.mem.xact_rep.bits.t_type === X_REP_READ_EXCLUSIVE)
+  data_arb.io.in(0).valid := io.mem.xact_rep.valid && (io.mem.xact_rep.bits.x_type === xactReplyReadShared || io.mem.xact_rep.bits.x_type === xactReplyReadExclusive)
 
   // load hits
   data_arb.io.in(4).bits.offset := io.cpu.req_idx(offsetmsb,ramindexlsb)
diff --git a/rocket/src/main/scala/uncore.scala b/rocket/src/main/scala/uncore.scala
index fa6e2b1e..8dc88d44 100644
--- a/rocket/src/main/scala/uncore.scala
+++ b/rocket/src/main/scala/uncore.scala
@@ -74,7 +74,7 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
     val p_rep_tile_id   = Bits(TILE_ID_BITS, OUTPUT)
     val tile_xact_id    = Bits(TILE_XACT_ID_BITS, OUTPUT)
     val sharer_count    = Bits(TILE_ID_BITS+1, OUTPUT)
-    val t_type          = Bits(X_INIT_TYPE_BITS, OUTPUT)
+    val x_type          = Bits(X_INIT_TYPE_BITS, OUTPUT)
     val push_p_req      = Bits(ntiles, OUTPUT)
     val pop_p_rep       = Bits(ntiles, OUTPUT)
     val pop_p_rep_data  = Bits(ntiles, OUTPUT)
@@ -117,7 +117,7 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
   val s_idle :: s_ack :: s_mem :: s_probe :: s_busy :: Nil = Enum(5){ UFix() }
   val state = Reg(resetVal = s_idle)
   val addr_  = Reg{ UFix() }
-  val t_type_ = Reg{ Bits() }
+  val x_type_ = Reg{ Bits() }
   val init_tile_id_ = Reg{ Bits() }
   val tile_xact_id_ = Reg{ Bits() }
   val p_rep_count = if (ntiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2up(ntiles)))
@@ -138,7 +138,7 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
   io.p_rep_tile_id := p_rep_tile_id_
   io.tile_xact_id := tile_xact_id_
   io.sharer_count := UFix(ntiles) // TODO: Broadcast only
-  io.t_type := t_type_
+  io.x_type := x_type_
 
   io.mem_req_cmd.valid              := Bool(false)
   io.mem_req_cmd.bits.rw := Bool(false)
@@ -148,7 +148,7 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
   io.mem_req_data.bits.data := UFix(0)
   io.mem_req_lock := Bool(false)
   io.probe_req.valid := Bool(false)
-  io.probe_req.bits.p_type := getProbeRequestType(t_type_, UFix(0))
+  io.probe_req.bits.p_type := getProbeRequestType(x_type_, UFix(0))
   io.probe_req.bits.global_xact_id  := UFix(id)
   io.probe_req.bits.address := addr_
   io.push_p_req      := Bits(0, width = ntiles)
@@ -164,11 +164,11 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
     is(s_idle) {
       when( io.alloc_req.valid && io.can_alloc ) {
         addr_ := io.alloc_req.bits.xact_init.address
-        t_type_ := io.alloc_req.bits.xact_init.t_type
+        x_type_ := io.alloc_req.bits.xact_init.x_type
         init_tile_id_ := io.alloc_req.bits.tile_id
         tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id
         x_init_data_needs_write := hasData(io.alloc_req.bits.xact_init)
-        x_needs_read := needsMemRead(io.alloc_req.bits.xact_init.t_type, UFix(0))
+        x_needs_read := needsMemRead(io.alloc_req.bits.xact_init.x_type, UFix(0))
         if(ntiles > 1) p_rep_count := UFix(ntiles-1)
         val p_req_initial_flags = ~( UFix(1) << io.alloc_req.bits.tile_id ) //TODO: Broadcast only
         p_req_flags := p_req_initial_flags
@@ -226,7 +226,7 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
       } . elsewhen (x_needs_read) {    
         doMemReqRead(io.mem_req_cmd, x_needs_read)
       } . otherwise { 
-        state := Mux(needsAckReply(t_type_, UFix(0)), s_ack, s_busy)
+        state := Mux(needsAckReply(x_type_, UFix(0)), s_ack, s_busy)
       }
     }
     is(s_ack) {
@@ -251,7 +251,7 @@ abstract class CoherenceHub(ntiles: Int) extends Component with CoherencePolicy
 class CoherenceHubNull extends CoherenceHub(1) with ThreeStateIncoherence 
 {
   val x_init = io.tiles(0).xact_init
-  val is_write = x_init.bits.t_type === X_INIT_WRITE_UNCACHED
+  val is_write = x_init.bits.x_type === xactInitWriteUncached
   x_init.ready := io.mem.req_cmd.ready && !(is_write && io.mem.resp.valid) //stall write req/resp to handle previous read resp
   io.mem.req_cmd.valid   := x_init.valid && !(is_write && io.mem.resp.valid)
   io.mem.req_cmd.bits.rw    := is_write
@@ -260,7 +260,7 @@ class CoherenceHubNull extends CoherenceHub(1) with ThreeStateIncoherence
   io.mem.req_data <> io.tiles(0).xact_init_data
 
   val x_rep = io.tiles(0).xact_rep
-  x_rep.bits.t_type := Mux(io.mem.resp.valid, X_REP_READ_EXCLUSIVE, X_REP_WRITE_UNCACHED)
+  x_rep.bits.x_type := Mux(io.mem.resp.valid, xactReplyReadExclusive, xactReplyWriteUncached)
   x_rep.bits.tile_xact_id := Mux(io.mem.resp.valid, io.mem.resp.bits.tag, x_init.bits.tile_xact_id)
   x_rep.bits.global_xact_id := UFix(0) // don't care
   x_rep.bits.data := io.mem.resp.bits.data
@@ -283,7 +283,7 @@ class CoherenceHubBroadcast(ntiles: Int) extends CoherenceHub(ntiles) with FourS
   val addr_arr           = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS-OFFSET_BITS)} }
   val init_tile_id_arr   = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
   val tile_xact_id_arr   = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_XACT_ID_BITS)} }
-  val t_type_arr         = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=X_INIT_TYPE_BITS)} }
+  val x_type_arr         = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=X_INIT_TYPE_BITS)} }
   val sh_count_arr       = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
   val send_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
 
@@ -300,7 +300,7 @@ class CoherenceHubBroadcast(ntiles: Int) extends CoherenceHub(ntiles) with FourS
     addr_arr(i)           := t.addr
     init_tile_id_arr(i)   := t.init_tile_id
     tile_xact_id_arr(i)   := t.tile_xact_id
-    t_type_arr(i)         := t.t_type
+    x_type_arr(i)         := t.x_type
     sh_count_arr(i)       := t.sharer_count
     send_x_rep_ack_arr(i) := t.send_x_rep_ack
     t.xact_finish         := do_free_arr(i)
@@ -337,19 +337,19 @@ class CoherenceHubBroadcast(ntiles: Int) extends CoherenceHub(ntiles) with FourS
   val ack_idx = PriorityEncoder(send_x_rep_ack_arr.toBits)
   for( j <- 0 until ntiles ) {
     val rep = io.tiles(j).xact_rep
-    rep.bits.t_type := UFix(0)
+    rep.bits.x_type := UFix(0)
     rep.bits.tile_xact_id := UFix(0)
     rep.bits.global_xact_id := UFix(0)
     rep.bits.data := io.mem.resp.bits.data
     rep.bits.require_ack := Bool(true)
     rep.valid := Bool(false)
     when(io.mem.resp.valid && (UFix(j) === init_tile_id_arr(mem_idx))) {
-      rep.bits.t_type := getTransactionReplyType(t_type_arr(mem_idx), sh_count_arr(mem_idx))
+      rep.bits.x_type := getTransactionReplyType(x_type_arr(mem_idx), sh_count_arr(mem_idx))
       rep.bits.tile_xact_id := tile_xact_id_arr(mem_idx)
       rep.bits.global_xact_id := mem_idx
       rep.valid := Bool(true)
     } . otherwise {
-      rep.bits.t_type := getTransactionReplyType(t_type_arr(ack_idx), sh_count_arr(ack_idx))
+      rep.bits.x_type := getTransactionReplyType(x_type_arr(ack_idx), sh_count_arr(ack_idx))
       rep.bits.tile_xact_id := tile_xact_id_arr(ack_idx)
       rep.bits.global_xact_id := ack_idx
       when (UFix(j) === init_tile_id_arr(ack_idx)) {