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tilelink: fix RAMModel handling of AMOs on early source reuse (#897)

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Wesley W. Terpstra 2017-07-27 11:07:13 -07:00 committed by Andrew Waterman
parent 9804bdc34e
commit 0ab5cb67b3
1 changed files with 2 additions and 2 deletions
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src/main/scala/tilelink/RAMModel.scala
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@ -231,8 +231,8 @@ class TLRAMModel(log: String = "")(implicit p: Parameters) extends LazyModule
val d_crc_new = FillInterleaved(8, d_mask) & d.data val d_crc_new = FillInterleaved(8, d_mask) & d.data
val d_crc = CRC(divisor, Cat(d_crc_acc, d_crc_new), 16 + beatBytes*8) val d_crc = CRC(divisor, Cat(d_crc_acc, d_crc_new), 16 + beatBytes*8)
val crc_bypass = if (edge.manager.minLatency > 0) Bool(false) else a_fire && a.source === d.source val crc_bypass = if (edge.manager.minLatency > 0) Bool(false) else a_fire && a.source === d.source
val d_crc_valid = Mux(crc_bypass, a_crc_valid, crc_valid.read(d.source)) val d_crc_valid = Mux(crc_bypass, a_crc_valid, crc_valid.read(d.source)) holdUnless d_first
val d_crc_check = Mux(crc_bypass, a_crc, crc.read(d.source)) val d_crc_check = Mux(crc_bypass, a_crc, crc.read(d.source)) holdUnless d_first
val d_no_race_reg = Reg(Bool()) val d_no_race_reg = Reg(Bool())
val d_no_race = Wire(init = d_no_race_reg) val d_no_race = Wire(init = d_no_race_reg)