riscv/rocket-chip
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connect top level interrupts to coreplex

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This commit is contained in:
Colin Schmidt 2016-08-18 15:52:06 -07:00
parent 91a97d6773
commit 0a6c05a5d8
1 changed files with 2 additions and 0 deletions
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src/main/scala/RocketChip.scala
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@ -171,6 +171,8 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
asyncAxiFrom(io.bus_clk.get, io.bus_rst.get, io.bus_axi)
else io.bus_axi)
coreplex.io.interrupts <> io.interrupts
io.extra <> periphery.io.extra
p(ConnectExtraPorts)(io.extra, coreplex.io.extra, p)
}