subsystem: more buswrapper coupling methods

src/main/scala/subsystem/FrontBus.scala

@@ -17,29 +17,32 @@ class FrontBus(params: FrontBusParams, val crossing: SubsystemClockCrossing = Sy
     with HasTLXbarPhy
     with HasCrossing {
 
-  def fromPort[D,U,E,B <: Data](
+  def fromPort[D,U,E,B <: Data]
-        name: Option[String] = None,
+      (name: Option[String] = None, buffers: Int = 1)
-        buffers: Int = 1)
+      (gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] =
-      (gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle]): InwardNodeHandle[D,U,E,B] = {
+        TLIdentity.gen): InwardNodeHandle[D,U,E,B] = {
     from("port" named name) {
       val nodes = TLFIFOFixer(TLFIFOFixer.all) +: TLBuffer.chain(buffers)
       inwardNode :=* nodes.reduce(_ :=* _) :=* gen
     }
   }
 
-  def fromMaster(name: Option[String] = None, buffers: Int = 1)
+  def fromMasterNode( name: Option[String] = None, buffers: Int = 1)(gen: TLOutwardNode) { 
-                (gen: => TLNode): TLInwardNode = {
+    from("master" named name) { bufferFrom(buffers) :=* gen }
-    from("master" named name) {
-      inwardNode :=* TLBuffer.chain(buffers).reduce(_ :=* _) :=* gen
   }
+
+  def fromMaster[D,U,E,B <: Data]
+      (name: Option[String] = None, buffers: Int = 1)
+      (gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] =
+        TLIdentity.gen): InwardNodeHandle[D,U,E,B] = {
+    from("master" named name) { bufferFrom(buffers) :=* gen }
   }
 
   def fromCoherentChip(gen: => TLNode): TLInwardNode = {
     from("coherent_subsystem") { inwardNode :=* gen }
   }
 
-  def toSystemBus(buffer: BufferParams = BufferParams.none)
+  def toSystemBus(buffer: BufferParams = BufferParams.none)(gen: => TLInwardNode) {
-                 (gen: => TLInwardNode) {
     to("sbus") { gen :=* TLBuffer(buffer) :=* outwardNode }
   }
 }

src/main/scala/subsystem/MemoryBus.scala

@@ -44,33 +44,34 @@ case object MemoryBusKey extends Field[MemoryBusParams]
 class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "memory_bus")(p)
     with HasTLXbarPhy {
 
-  private def bufferTo(buffer: BufferParams): TLOutwardNode =
-    TLBuffer(buffer) :*= delayNode :*= outwardNode
-
   def fromCoherenceManager(
         name: Option[String] = None,
         buffer: BufferParams = BufferParams.none)
       (gen: => TLNode): TLInwardNode = {
     from("coherence_manager" named name) {
-      inwardNode :*= TLBuffer(buffer) :*= gen
+      inwardNode := TLBuffer(buffer) := gen
     }
   }
 
-  def toDRAMController[D,U,E,B <: Data](
+  def toDRAMController[D,U,E,B <: Data]
-        name: Option[String] = None,
+      (name: Option[String] = None, buffer: BufferParams = BufferParams.none)
-        buffer: BufferParams = BufferParams.none)
+      (gen: => NodeHandle[ TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle, D,U,E,B] =
-      (gen: => NodeHandle[
+        TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
-                TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,
-                D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
     to("memory_controller" named name) { gen := bufferTo(buffer) }
   }
 
-  def toVariableWidthSlave(
+  def toVariableWidthSlave[D,U,E,B <: Data]
-        name: Option[String] = None,
+      (name: Option[String] = None, buffer: BufferParams = BufferParams.none)
-        buffer: BufferParams = BufferParams.none)
+      (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
-      (gen: => TLNode): TLOutwardNode = {
+        TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
-    to("slave" named name) {
+    to("slave" named name) { gen :*= fragmentTo(buffer) }
-      gen :*= TLFragmenter(params.beatBytes, params.blockBytes) :*= bufferTo(buffer)
   }
+
+  def toFixedWidthSlave[D,U,E,B <: Data]
+      (name: Option[String] = None, buffer: BufferParams = BufferParams.none)
+      (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
+        TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
+    to("slave" named name) { gen :*= fixedWidthTo(buffer) }
   }
+
 }

src/main/scala/subsystem/PeripheryBus.scala

@@ -21,18 +21,6 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
     with HasTLXbarPhy
     with HasCrossing {
 
-  private def bufferTo(buffer: BufferParams): TLOutwardNode =
-    TLBuffer(buffer) :*= delayNode :*= outwardNode
-
-  private def bufferTo(buffers: Int): TLOutwardNode =
-    TLBuffer.chain(buffers).foldRight(delayNode)(_ :*= _) :*= outwardNode
-
-  private def fragmentTo(minSize: Int, maxSize: Int, buffer: BufferParams): TLOutwardNode =
-    TLFragmenter(minSize, maxSize) :*= bufferTo(buffer)
-
-  private def fixedWidthTo(buffer: BufferParams): TLOutwardNode =
-    TLWidthWidget(params.beatBytes) :*= bufferTo(buffer)
-
   def toSlave[D,U,E,B <: Data](
         name: Option[String] = None,
         buffer: BufferParams = BufferParams.none)
@@ -42,6 +30,15 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
     to("slave" named name) { gen :*= bufferTo(buffer) }
   }
 
+  def toVariableWidthSlaveNode(
+        name: Option[String] = None,
+        buffer: BufferParams = BufferParams.none)
+      (gen: TLInwardNode) {
+    to("slave" named name) {
+      gen :*= fragmentTo(params.beatBytes, params.blockBytes, buffer)
+    }
+  }
+
   def toVariableWidthSlave[D,U,E,B <: Data](
         name: Option[String] = None,
         buffer: BufferParams = BufferParams.none)
@@ -53,6 +50,13 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
     }
   }
 
+  def toFixedWidthSlaveNode(
+        name: Option[String] = None,
+        buffer: BufferParams = BufferParams.none)
+      (gen: TLInwardNode) {
+    to("slave" named name) { gen :*= fixedWidthTo(buffer) }
+  }
+
   def toFixedWidthSlave[D,U,E,B <: Data](
         name: Option[String] = None,
         buffer: BufferParams = BufferParams.none)
@@ -62,6 +66,16 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
     to("slave" named name) { gen :*= fixedWidthTo(buffer) }
   }
 
+  def toFixedWidthSingleBeatSlaveNode(
+        widthBytes: Int,
+        name: Option[String] = None,
+        buffer: BufferParams = BufferParams.none)
+      (gen: TLInwardNode) {
+    to("slave" named name) {
+      gen :*= TLFragmenter(widthBytes, params.blockBytes) :*= fixedWidthTo(buffer)
+    }
+  }
+
   def toFixedWidthSingleBeatSlave[D,U,E,B <: Data](
         widthBytes: Int,
         name: Option[String] = None,
@@ -108,7 +122,7 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
         name: Option[String] = None,
         buffer: BufferParams = BufferParams.none)
       (gen: => TLNode): TLInwardNode = {
-    from("master" named name) { inwardNode :*= TLBuffer(buffer) :*= gen }
+    from("master" named name) { bufferFrom(buffer) :=* gen }
   }
 
 
@@ -116,10 +130,8 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
         name: Option[String] = None,
         buffers: Int = 0)
       (gen: => TLNode): TLOutwardNode = {
-    to("tile" named name) {
+    to("tile" named name) { FlipRendering { implicit p =>
-      FlipRendering { implicit p =>
       gen :*= bufferTo(buffers)
-      }
+    }}
-    }
   }
 }

src/main/scala/subsystem/SystemBus.scala

@@ -20,12 +20,6 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
 
   def busView = master_splitter.node.edges.in.head
 
-  private def bufferTo(buffer: BufferParams): TLOutwardNode =
-    TLBuffer(buffer) :*= delayNode :*= outwardNode
-
-  private def fixedWidthTo(buffer: BufferParams): TLOutwardNode =
-    TLWidthWidget(params.beatBytes) :*= bufferTo(buffer)
-
   def toPeripheryBus(buffer: BufferParams = BufferParams.none)
                     (gen: => TLNode): TLOutwardNode = {
     to("pbus") {
@@ -37,30 +31,34 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
   }
 
   def toMemoryBus(gen: => TLInwardNode) {
-    to("mbus") { gen :*= delayNode :*= outwardNode }
+    to("mbus") { gen := delayNode := outwardNode }
   }
 
-  def toSlave(name: Option[String] = None, buffer: BufferParams = BufferParams.default)
+  def toSlave[D,U,E,B <: Data]
-             (gen: => TLNode): TLOutwardNode = {
+      (name: Option[String] = None, buffer: BufferParams = BufferParams.default)
+      (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
+        TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
     to("slave" named name) { gen :*= bufferTo(buffer) }
   }
  
-  def toSplitSlave(name: Option[String] = None)
+  def toSplitSlave[D,U,E,B <: Data]
-                  (gen: => TLNode): TLOutwardNode = {
+      (name: Option[String] = None)
+      (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
+        TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
     to("slave" named name) { gen :=* master_splitter.node }
   }
 
-  def toFixedWidthSlave(
+  def toFixedWidthSlave[D,U,E,B <: Data]
-        name: Option[String] = None,
+      (name: Option[String] = None, buffer: BufferParams = BufferParams.none)
-        buffer: BufferParams = BufferParams.none)
+      (gen: =>  NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
-      (gen: => TLNode): TLOutwardNode = {
+        TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
     to("slave" named name) { gen :*= fixedWidthTo(buffer) }
   }
 
-  def toVariableWidthSlave(
+  def toVariableWidthSlave[D,U,E,B <: Data]
-        name: Option[String] = None,
+      (name: Option[String] = None, buffer: BufferParams = BufferParams.default)
-        buffer: BufferParams = BufferParams.default)
+      (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
-      (gen: => TLNode): TLOutwardNode = {
+        TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
     to("slave" named name) {
       gen :*= TLFragmenter(params.beatBytes, params.blockBytes) :*= bufferTo(buffer)
     }
@@ -70,10 +68,8 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
     from("front_bus") { master_splitter.node :=* gen }
   }
 
-  def fromTile(
+  def fromTile
-        name: Option[String],
+      (name: Option[String], buffers: Int = 0, cork: Option[Boolean] = None)
-        buffers: Int = 0,
-        cork: Option[Boolean] = None)
       (gen: => TLNode): TLInwardNode = {
     from("tile" named name) {
       (List(master_splitter.node, TLFIFOFixer(TLFIFOFixer.allUncacheable)) ++ TLBuffer.chain(buffers))
@@ -81,17 +77,17 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
     }
   }
 
-  def toFixedWidthPort[D,U,E,B <: Data](
+  def toFixedWidthPort[D,U,E,B <: Data]
-        name: Option[String] = None,
+      (name: Option[String] = None, buffer: BufferParams = BufferParams.default)
-        buffer: BufferParams = BufferParams.default)
+      (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
-      (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B]): OutwardNodeHandle[D,U,E,B] = {
+        TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
     to("port" named name) { gen := fixedWidthTo(buffer) }
   }
 
-  def fromPort[D,U,E,B <: Data](
+  def fromPort[D,U,E,B <: Data]
-        name: Option[String] = None,
+      (name: Option[String] = None, buffers: Int = 0)
-        buffers: Int = 0)
+      (gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] =
-      (gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle]): InwardNodeHandle[D,U,E,B] = {
+        TLIdentity.gen): InwardNodeHandle[D,U,E,B] = {
     from("port" named name) {
       (List(
         master_splitter.node,
@@ -100,22 +96,21 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
     }
   }
 
-  def fromCoherentMaster(
+  def fromCoherentMaster[D,U,E,B <: Data]
-        name: Option[String] = None,
+      (name: Option[String] = None, buffers: Int = 0)
-        buffers: Int = 0)
+      (gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] =
-      (gen: => TLNode): TLInwardNode = {
+        TLIdentity.gen): InwardNodeHandle[D,U,E,B] = {
     from("coherent_master" named name) {
       (inwardNode
-        :=* TLFIFOFixer(TLFIFOFixer.all)
+        :=* TLBuffer.chain(buffers).foldLeft(TLFIFOFixer(TLFIFOFixer.all))(_ :=* _)
-        :=* TLBuffer.chain(buffers).reduce(_ :=* _)
         :=* gen)
     }
   }
 
-  def fromMaster(
+  def fromMaster[D,U,E,B <: Data]
-        name: Option[String] = None,
+      (name: Option[String] = None, buffers: Int = 0)
-        buffers: Int = 0)
+      (gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] =
-      (gen: => TLNode): TLInwardNode = {
+        TLIdentity.gen): InwardNodeHandle[D,U,E,B] = {
     from("master" named name) {
       (master_splitter.node
         :=* TLFIFOFixer(TLFIFOFixer.all)

src/main/scala/tilelink/BusWrapper.scala

@@ -29,6 +29,28 @@ abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implici
   protected def inwardNode: TLInwardNode
   protected def outwardNode: TLOutwardNode
 
+  protected def bufferFrom(buffer: BufferParams): TLInwardNode =
+    inwardNode :=* TLBuffer(buffer)
+
+  protected def bufferFrom(buffers: Int): TLInwardNode =
+    TLBuffer.chain(buffers).foldLeft(inwardNode)(_ :=* _)
+
+  protected def bufferTo(buffer: BufferParams): TLOutwardNode =
+    TLBuffer(buffer) :*= delayNode :*= outwardNode
+
+  protected def bufferTo(buffers: Int): TLOutwardNode =
+    TLBuffer.chain(buffers).foldRight(delayNode)(_ :*= _) :*= outwardNode
+
+  protected def fixedWidthTo(buffer: BufferParams): TLOutwardNode =
+    TLWidthWidget(beatBytes) :*= bufferTo(buffer)
+
+  protected def fragmentTo(buffer: BufferParams): TLOutwardNode =
+    TLFragmenter(beatBytes, blockBytes) :*= bufferTo(buffer)
+
+  protected def fragmentTo(minSize: Int, maxSize: Int, buffer: BufferParams): TLOutwardNode =
+    TLFragmenter(minSize, maxSize) :*= bufferTo(buffer)
+
+
   protected def delayNode(implicit p: Parameters): TLNode = {
     val delayProb = p(TLBusDelayProbability)
     if (delayProb > 0.0) {