riscv/rocket-chip
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Merge pull request #544 from ucb-bar/jchang

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Added access function
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Jacob Chang 2017-02-02 14:56:23 -08:00 committed by GitHub
commit 094b3bc2b1
2 changed files with 11 additions and 0 deletions
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2
src/main/scala/diplomacy/Parameters.scala
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@ -39,6 +39,8 @@ case class IdRange(start: Int, end: Int)
def shift(x: Int) = IdRange(start+x, end+x) def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start def size = end - start
def range = start until end
} }
// An potentially empty inclusive range of 2-powers [min, max] (in bytes) // An potentially empty inclusive range of 2-powers [min, max] (in bytes)

9
src/main/scala/uncore/tilelink2/Edges.scala
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@ -158,6 +158,15 @@ class TLEdge(
} }
} }
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt = def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) UInt(0) else x(log2Ceil(manager.beatBytes)-1, 0) if (manager.beatBytes == 1) UInt(0) else x(log2Ceil(manager.beatBytes)-1, 0)