diff --git a/src/main/scala/diplomacy/Parameters.scala b/src/main/scala/diplomacy/Parameters.scala
index d81ce4b0..fd9d9f0b 100644
--- a/src/main/scala/diplomacy/Parameters.scala
+++ b/src/main/scala/diplomacy/Parameters.scala
@@ -39,6 +39,8 @@ case class IdRange(start: Int, end: Int)
 
   def shift(x: Int) = IdRange(start+x, end+x)
   def size = end - start
+  
+  def range = start until end
 }
 
 // An potentially empty inclusive range of 2-powers [min, max] (in bytes)
diff --git a/src/main/scala/uncore/tilelink2/Edges.scala b/src/main/scala/uncore/tilelink2/Edges.scala
index 886902d7..14800fe9 100644
--- a/src/main/scala/uncore/tilelink2/Edges.scala
+++ b/src/main/scala/uncore/tilelink2/Edges.scala
@@ -158,6 +158,15 @@ class TLEdge(
     }
   }
 
+  def source(x: TLDataChannel): UInt = {
+    x match {
+      case a: TLBundleA => a.source
+      case b: TLBundleB => b.source
+      case c: TLBundleC => c.source
+      case d: TLBundleD => d.source
+    }
+  }
+
   def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
   def addr_lo(x: UInt): UInt =
     if (manager.beatBytes == 1) UInt(0) else x(log2Ceil(manager.beatBytes)-1, 0)