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Changed label for DCache and ICache error covers + take away exclusio… (#1155)

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* Changed label for DCache and ICache error covers + take away exclusion that shouldn't be there

* rocket: add d-channel error to I$
This commit is contained in:
Jacob Chang 2017-12-13 20:16:36 -08:00 committed by GitHub
parent a542ae687e
commit 09160d0cd5
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 12 additions and 13 deletions
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17
src/main/scala/rocket/DCache.scala
View File

@ -803,8 +803,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
if (usingDataScratchpad) {
val data_error_cover = Seq(
CoverBoolean(!data_error, Seq("no_data_error")),
CoverBoolean(data_error && !data_error_uncorrectable, Seq("correctable_data_error")),
CoverBoolean(data_error && data_error_uncorrectable, Seq("uncorrectable_data_error")))
CoverBoolean(data_error && !data_error_uncorrectable, Seq("data_correctable_error")),
CoverBoolean(data_error && data_error_uncorrectable, Seq("data_uncorrectable_error")))
val request_source = Seq(
CoverBoolean(s2_isSlavePortAccess, Seq("from_TL")),
CoverBoolean(!s2_isSlavePortAccess, Seq("from_CPU")))
@ -815,11 +815,10 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
"MemorySystem;;Scratchpad Memory Bit Flip Cross Covers"))
} else {
val data_error_cover = Seq(CoverBoolean(s2_valid_data_error, Seq("data_error")))
val data_error_type = Seq(
CoverBoolean(!s2_data_error_uncorrectable, Seq("correctable")),
CoverBoolean(s2_data_error_uncorrectable, Seq("uncorrectable")))
CoverBoolean(!s2_valid_data_error, Seq("no_data_error")),
CoverBoolean(s2_valid_data_error && !s2_data_error_uncorrectable, Seq("data_correctable_error")),
CoverBoolean(s2_valid_data_error && s2_data_error_uncorrectable, Seq("data_uncorrectable_error")))
val data_error_dirty = Seq(
CoverBoolean(!s2_victim_dirty, Seq("data_clean")),
CoverBoolean(s2_victim_dirty, Seq("data_dirty")))
@ -832,10 +831,10 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
}
val tag_error_cover = Seq(
CoverBoolean( !metaArb.io.in(1).valid, Seq("no_tag_error")),
CoverBoolean( metaArb.io.in(1).valid && !s2_meta_error_uncorrectable, Seq("correctable_tag_error")),
CoverBoolean( metaArb.io.in(1).valid && s2_meta_error_uncorrectable, Seq("uncorrectable_tag_error")))
CoverBoolean( metaArb.io.in(1).valid && !s2_meta_error_uncorrectable, Seq("tag_correctable_error")),
CoverBoolean( metaArb.io.in(1).valid && s2_meta_error_uncorrectable, Seq("tag_uncorrectable_error")))
cover(new CrossProperty(
Seq(data_error_cover, data_error_type, data_error_dirty, request_source, tag_error_cover),
Seq(data_error_type, data_error_dirty, request_source, tag_error_cover),
Seq(),
"MemorySystem;;Cache Memory Bit Flip Cross Covers"))
}

8
src/main/scala/rocket/ICache.scala
View File

@ -180,6 +180,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
when (refill_done) {
val enc_tag = tECC.encode(Cat(tl_out.d.bits.error, refill_tag))
tag_array.write(refill_idx, Vec.fill(nWays)(enc_tag), Seq.tabulate(nWays)(repl_way === _))
ccover(tl_out.d.bits.error, "D_ERROR", "I$ D-channel error")
}
val vb_array = Reg(init=Bits(0, nSets*nWays))
@ -411,8 +413,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
val mem_active_valid = Seq(CoverBoolean(s2_valid, Seq("mem_active")))
val data_error = Seq(
CoverBoolean(!s2_data_decoded.correctable && !s2_data_decoded.uncorrectable, Seq("no_data_error")),
CoverBoolean(s2_data_decoded.correctable, Seq("correctable_bit_error")),
CoverBoolean(s2_data_decoded.uncorrectable, Seq("uncorrectable_bit_error")))
CoverBoolean(s2_data_decoded.correctable, Seq("data_correctable_error")),
CoverBoolean(s2_data_decoded.uncorrectable, Seq("data_uncorrectable_error")))
val request_source = Seq(
CoverBoolean(!s2_slaveValid, Seq("from_CPU")),
CoverBoolean(s2_slaveValid, Seq("from_TL"))
@ -431,8 +433,6 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
Seq(
// tag error cannot occur in ITIM mode
Seq("tag_error", "ITIM_mode"),
// tag is only parity check
Seq("tag_error", "uncorrectable_bit_error"),
// Can only respond to TL in ITIM mode
Seq("from_TL", "cache_mode")
),