From 09160d0cd59cf74366541270a225985812277343 Mon Sep 17 00:00:00 2001 From: Jacob Chang Date: Wed, 13 Dec 2017 20:16:36 -0800 Subject: [PATCH] =?UTF-8?q?Changed=20label=20for=20DCache=20and=20ICache?= =?UTF-8?q?=20error=20covers=20+=20take=20away=20exclusio=E2=80=A6=20(#115?= =?UTF-8?q?5)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Changed label for DCache and ICache error covers + take away exclusion that shouldn't be there * rocket: add d-channel error to I$ --- src/main/scala/rocket/DCache.scala | 17 ++++++++--------- src/main/scala/rocket/ICache.scala | 8 ++++---- 2 files changed, 12 insertions(+), 13 deletions(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index eaa93c37..e3982151 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -803,8 +803,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { if (usingDataScratchpad) { val data_error_cover = Seq( CoverBoolean(!data_error, Seq("no_data_error")), - CoverBoolean(data_error && !data_error_uncorrectable, Seq("correctable_data_error")), - CoverBoolean(data_error && data_error_uncorrectable, Seq("uncorrectable_data_error"))) + CoverBoolean(data_error && !data_error_uncorrectable, Seq("data_correctable_error")), + CoverBoolean(data_error && data_error_uncorrectable, Seq("data_uncorrectable_error"))) val request_source = Seq( CoverBoolean(s2_isSlavePortAccess, Seq("from_TL")), CoverBoolean(!s2_isSlavePortAccess, Seq("from_CPU"))) @@ -815,11 +815,10 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { "MemorySystem;;Scratchpad Memory Bit Flip Cross Covers")) } else { - val data_error_cover = Seq(CoverBoolean(s2_valid_data_error, Seq("data_error"))) - val data_error_type = Seq( - CoverBoolean(!s2_data_error_uncorrectable, Seq("correctable")), - CoverBoolean(s2_data_error_uncorrectable, Seq("uncorrectable"))) + CoverBoolean(!s2_valid_data_error, Seq("no_data_error")), + CoverBoolean(s2_valid_data_error && !s2_data_error_uncorrectable, Seq("data_correctable_error")), + CoverBoolean(s2_valid_data_error && s2_data_error_uncorrectable, Seq("data_uncorrectable_error"))) val data_error_dirty = Seq( CoverBoolean(!s2_victim_dirty, Seq("data_clean")), CoverBoolean(s2_victim_dirty, Seq("data_dirty"))) @@ -832,10 +831,10 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { } val tag_error_cover = Seq( CoverBoolean( !metaArb.io.in(1).valid, Seq("no_tag_error")), - CoverBoolean( metaArb.io.in(1).valid && !s2_meta_error_uncorrectable, Seq("correctable_tag_error")), - CoverBoolean( metaArb.io.in(1).valid && s2_meta_error_uncorrectable, Seq("uncorrectable_tag_error"))) + CoverBoolean( metaArb.io.in(1).valid && !s2_meta_error_uncorrectable, Seq("tag_correctable_error")), + CoverBoolean( metaArb.io.in(1).valid && s2_meta_error_uncorrectable, Seq("tag_uncorrectable_error"))) cover(new CrossProperty( - Seq(data_error_cover, data_error_type, data_error_dirty, request_source, tag_error_cover), + Seq(data_error_type, data_error_dirty, request_source, tag_error_cover), Seq(), "MemorySystem;;Cache Memory Bit Flip Cross Covers")) } diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index 5d6efc28..f9f729ce 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -180,6 +180,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) when (refill_done) { val enc_tag = tECC.encode(Cat(tl_out.d.bits.error, refill_tag)) tag_array.write(refill_idx, Vec.fill(nWays)(enc_tag), Seq.tabulate(nWays)(repl_way === _)) + + ccover(tl_out.d.bits.error, "D_ERROR", "I$ D-channel error") } val vb_array = Reg(init=Bits(0, nSets*nWays)) @@ -411,8 +413,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) val mem_active_valid = Seq(CoverBoolean(s2_valid, Seq("mem_active"))) val data_error = Seq( CoverBoolean(!s2_data_decoded.correctable && !s2_data_decoded.uncorrectable, Seq("no_data_error")), - CoverBoolean(s2_data_decoded.correctable, Seq("correctable_bit_error")), - CoverBoolean(s2_data_decoded.uncorrectable, Seq("uncorrectable_bit_error"))) + CoverBoolean(s2_data_decoded.correctable, Seq("data_correctable_error")), + CoverBoolean(s2_data_decoded.uncorrectable, Seq("data_uncorrectable_error"))) val request_source = Seq( CoverBoolean(!s2_slaveValid, Seq("from_CPU")), CoverBoolean(s2_slaveValid, Seq("from_TL")) @@ -431,8 +433,6 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) Seq( // tag error cannot occur in ITIM mode Seq("tag_error", "ITIM_mode"), - // tag is only parity check - Seq("tag_error", "uncorrectable_bit_error"), // Can only respond to TL in ITIM mode Seq("from_TL", "cache_mode") ),