riscv/rocket-chip
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Fixed btb/icache bugs regarding resp mask, fw==1

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This commit is contained in:
Christopher Celio 2014-10-20 18:45:23 -07:00
parent 91efdc379b
commit 08d2c13330
2 changed files with 15 additions and 7 deletions
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12
rocket/src/main/scala/btb.scala
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@ -196,9 +196,9 @@ class BTB extends Module with BTBParameters {
useRAS(waddr) := r_update.bits.isReturn
isJump(waddr) := r_update.bits.isJump
if (params(FetchWidth) == 1) {
brIdx(waddr) := UInt(0)
brIdx(waddr) := UInt(0)
} else {
brIdx(waddr) := r_update.bits.br_pc >> log2Up(params(CoreInstBits)/8)
brIdx(waddr) := r_update.bits.br_pc >> log2Up(params(CoreInstBits)/8)
}
}
@ -226,8 +226,14 @@ class BTB extends Module with BTBParameters {
io.resp.bits.taken := io.resp.valid
io.resp.bits.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts))
io.resp.bits.entry := OHToUInt(hits)
io.resp.bits.mask := Cat((UInt(1) << brIdx(io.resp.bits.entry))-1, UInt(1))
io.resp.bits.bridx := brIdx(io.resp.bits.entry)
if (params(FetchWidth) == 1) {
io.resp.bits.mask := UInt(1)
} else {
io.resp.bits.mask := Mux(io.resp.valid, Cat((UInt(1) << brIdx(io.resp.bits.entry))-1, UInt(1)),
((UInt(1) << UInt(params(FetchWidth)))-UInt(1)))
// val all_ones = UInt((1 << coreFetchWidth)-1)
}
if (nBHT > 0) {
val bht = new BHT(nBHT)

8
rocket/src/main/scala/icache.scala
View File

@ -58,9 +58,10 @@ class Frontend extends FrontendModule
val s2_xcpt_if = Reg(init=Bool(false))
val msb = vaddrBits-1
val lsb = log2Up(coreFetchWidth*coreInstBytes)
val btbTarget = Cat(btb.io.resp.bits.target(msb), btb.io.resp.bits.target)
val ntpc_0 = s1_pc + UInt(coreInstBytes)
val ntpc = Cat(s1_pc(msb) & ntpc_0(msb), ntpc_0(msb,0))
val ntpc_0 = s1_pc + UInt(coreInstBytes*coreFetchWidth)
val ntpc = Cat(s1_pc(msb) & ntpc_0(msb), ntpc_0(msb,lsb), Bits(0,lsb)) // unsure
val icmiss = s2_valid && !icache.io.resp.valid
val predicted_npc = Mux(btb.io.resp.bits.taken, btbTarget, ntpc)
val npc = Mux(icmiss, s2_pc, predicted_npc).toUInt
@ -115,7 +116,8 @@ class Frontend extends FrontendModule
val all_ones = UInt((1 << coreFetchWidth)-1)
val msk_pc = if (coreFetchWidth == 1) all_ones else all_ones << s2_pc(log2Up(coreFetchWidth) -1+2,2)
io.cpu.resp.bits.mask := msk_pc & btb.io.resp.bits.mask
// TODO what is the best way to handle the clock-gating of s2_btb_resp_bits?
io.cpu.resp.bits.mask := Mux(s2_btb_resp_valid, msk_pc & s2_btb_resp_bits.mask, msk_pc)
io.cpu.resp.bits.xcpt_ma := s2_pc(log2Up(coreInstBytes)-1,0) != UInt(0)
io.cpu.resp.bits.xcpt_if := s2_xcpt_if