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RocketTile: Create a wrapper for SyncRocketTile as well (#616)

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* RocketTile: Create a wrapper for SyncRocketTile as well

There is no guarantee that debugInterrupt is synchronous
to tlClk, even though it is true in the current implementation.
It will not be true in future implementations, as decoupling
this allows the debugInterrupt to be asserted across tlClk
gating/reset scenarios.

Therefore, even for SyncRocketTile, the debug interrupt needs to be
synchronized to coreClk, and for RationalRocketTile, 1 cycle
of synchronization is not sufficient.

Even though other interrupts may be synchronized, we just
synchronize them all to simplify the code at the expense of
a few cycles latency.

It could still be nice to use a parameter vs hard coding "3".

* RocketTile: Actually use the SyncRocketTile wrapper to get properly synchronized resets.
This commit is contained in:
Megan Wachs
2017-03-27 02:45:37 -07:00
committed by Wesley W. Terpstra
parent 722b0d521f
commit 08c4f7cea6
2 changed files with 43 additions and 7 deletions
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12
src/main/scala/coreplex/RocketTiles.scala
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@ -44,18 +44,18 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
crossing match {
case Synchronous => {
val tile = LazyModule(new RocketTile(c, i)(pWithExtra))
val wrapper = LazyModule(new SyncRocketTile(c, i)(pWithExtra))
val buffer = LazyModule(new TLBuffer)
val fixer = LazyModule(new TLFIFOFixer)
buffer.node :=* tile.masterNode
buffer.node :=* wrapper.masterNode
fixer.node :=* buffer.node
l1tol2.node :=* fixer.node
tile.slaveNode :*= cbus.node
tile.intNode := intBar.intnode
wrapper.slaveNode :*= cbus.node
wrapper.intNode := intBar.intnode
(io: HasRocketTilesBundle) => {
// leave clock as default (simpler for hierarchical PnR)
tile.module.io.hartid := UInt(i)
tile.module.io.resetVector := io.resetVector
wrapper.module.io.hartid := UInt(i)
wrapper.module.io.resetVector := io.resetVector
debugNode.bundleOut(0)(0) := debug.module.io.debugInterrupts(i)
}
}