riscv/rocket-chip
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interface cleanup, major pipeline changes

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This commit is contained in:
Rimas Avizienis
2011-11-01 17:59:27 -07:00
parent ace4c9d13c
commit 08b89e7710
7 changed files with 426 additions and 475 deletions
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89
rocket/src/main/scala/cpu.scala
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@ -39,57 +39,64 @@ class rocketProc extends Component
val io = new ioRocket();
val ctrl = new rocketCtrl();
val dpath = new rocketDpath();
val mem = new rocketMemory();
val wb = new rocketWriteback();
val dpath = new rocketDpath();
// val mem = new rocketMemory();
// val wb = new rocketWriteback();
dpath.io.host ^^ io.host;
dpath.io.debug ^^ io.debug;
// dpath.io.wb <> wb.io;
dpath.io.wb.wen <> wb.io.wb_wen;
dpath.io.wb.waddr <> wb.io.wb_waddr;
dpath.io.wb.wdata <> wb.io.wb_wdata;
dpath.io.imem.req_addr ^^ io.imem.req_addr;
dpath.io.imem.resp_data ^^ io.imem.resp_data;
ctrl.io.ctrl <> dpath.io.ctrl;
ctrl.io.dpath <> dpath.io.dpath;
// ctrl.io.mem <> mem.io;
ctrl.io.mem.mrq_val <> mem.io.mem_mrq_val;
ctrl.io.mem.mrq_cmd <> mem.io.mem_mrq_cmd;
ctrl.io.mem.mrq_type <> mem.io.mem_mrq_type;
ctrl.io.mem.mrq_deq <> mem.io.mem_mrq_deq;
ctrl.io.mem.xsdq_rdy <> mem.io.mem_xsdq_rdy;
ctrl.io.mem.xsdq_val <> mem.io.mem_xsdq_val;
ctrl.io.mem.dc_busy := !io.dmem.req_rdy;
ctrl.io.dpath <> dpath.io.ctrl;
ctrl.io.host.start ^^ io.host.start;
ctrl.io.imem ^^ io.imem;
dpath.io.imem.req_addr ^^ io.imem.req_addr;
dpath.io.imem.resp_data ^^ io.imem.resp_data;
dpath.io.host ^^ io.host;
dpath.io.debug ^^ io.debug;
ctrl.io.dmem ^^ io.dmem;
dpath.io.dmem ^^ io.dmem;
// FIXME
// io.console.bits := dpath.io.dpath.rs1(7,0);
io.console.bits := Bits(0,8);
io.console.valid := ctrl.io.console.valid;
ctrl.io.console.rdy := io.console.rdy;
// dpath.io.wb <> wb.io;
// dpath.io.wb.wen <> wb.io.wb_wen;
// dpath.io.wb.waddr <> wb.io.wb_waddr;
// dpath.io.wb.wdata <> wb.io.wb_wdata;
// ctrl.io.mem.mrq_val <> mem.io.mem_mrq_val;
// ctrl.io.mem.mrq_cmd <> mem.io.mem_mrq_cmd;
// ctrl.io.mem.mrq_type <> mem.io.mem_mrq_type;
// ctrl.io.mem.mrq_deq <> mem.io.mem_mrq_deq;
// ctrl.io.mem.xsdq_rdy <> mem.io.mem_xsdq_rdy;
// ctrl.io.mem.xsdq_val <> mem.io.mem_xsdq_val;
// ctrl.io.mem.dc_busy := !io.dmem.req_rdy;
// ctrl.io.console ^^ io.console;
ctrl.io.wb.waddr <> wb.io.wb_waddr;
ctrl.io.wb.wen <> wb.io.wb_wen;
// ctrl.io.wb.waddr <> wb.io.wb_waddr;
// ctrl.io.wb.wen <> wb.io.wb_wen;
// TODO: SHOULD BE THE FOLLOWING BUT NEED BETTER INTERFACE CHUNKS
// mem.io.dmem >< io.dmem;
mem.io.dmem_req_val ^^ io.dmem.req_val;
mem.io.dmem_req_rdy ^^ io.dmem.req_rdy;
mem.io.dmem_req_op ^^ io.dmem.req_op;
mem.io.dmem_req_addr ^^ io.dmem.req_addr;
mem.io.dmem_req_data ^^ io.dmem.req_data;
mem.io.dmem_req_wmask ^^ io.dmem.req_wmask;
mem.io.dmem_req_tag ^^ io.dmem.req_tag;
// mem.io.dmem_req_val ^^ io.dmem.req_val;
// mem.io.dmem_req_rdy ^^ io.dmem.req_rdy;
// mem.io.dmem_req_op ^^ io.dmem.req_op;
// mem.io.dmem_req_addr ^^ io.dmem.req_addr;
// mem.io.dmem_req_data ^^ io.dmem.req_data;
// mem.io.dmem_req_wmask ^^ io.dmem.req_wmask;
// mem.io.dmem_req_tag ^^ io.dmem.req_tag;
mem.io.dpath_rs2 <> dpath.io.dpath.rs2;
mem.io.dpath_waddr <> dpath.io.dpath.waddr;
mem.io.dpath_alu_out <> dpath.io.dpath.alu_out;
//
// mem.io.dpath_rs2 <> dpath.io.dpath.rs2;
// mem.io.dpath_waddr <> dpath.io.dpath.waddr;
// mem.io.dpath_alu_out <> dpath.io.dpath.alu_out;
wb.io.dmem_resp_val ^^ io.dmem.resp_val;
wb.io.dmem_resp_data ^^ io.dmem.resp_data;
wb.io.dmem_resp_tag ^^ io.dmem.resp_tag;
io.console.bits := dpath.io.dpath.rs1(7,0);
io.console.valid := ctrl.io.console.valid;
ctrl.io.console.rdy := io.console.rdy;
// wb.io.dmem_resp_val ^^ io.dmem.resp_val;
// wb.io.dmem_resp_data ^^ io.dmem.resp_data;
// wb.io.dmem_resp_tag ^^ io.dmem.resp_tag;
}
}