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add a single-entry queue in front of acquire and release for bufferless broadcast hub

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This commit is contained in:
Howard Mao 2016-07-05 10:18:25 -07:00
parent 67bac383e3
commit 06ed9c5794
1 changed files with 8 additions and 6 deletions
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14
uncore/src/main/scala/agents/Bufferless.scala
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@ -36,24 +36,26 @@ class BufferlessBroadcastHub(implicit p: Parameters) extends HierarchicalCoheren
io.inner.release.valid &&
io.irel().conflicts(io.iacq())
val iacq = Queue(io.inner.acquire, 1, pipe=true)
doInputRoutingWithAllocation(
in = io.inner.acquire,
in = iacq,
outs = trackerList.map(_.io.inner.acquire),
allocs = trackerList.map(_.io.alloc.iacq),
allocOverride = Some(!irel_vs_iacq_conflict))
io.outer.acquire.bits.data := io.inner.acquire.bits.data
io.outer.acquire.bits.data := iacq.bits.data
when (io.oacq().hasData()) {
io.outer.acquire.bits.addr_beat := io.inner.acquire.bits.addr_beat
io.outer.acquire.bits.addr_beat := iacq.bits.addr_beat
}
// Handle releases, which might be voluntary and might have data
val irel = Queue(io.inner.release, 1, pipe=true)
doInputRoutingWithAllocation(
in = io.inner.release,
in = irel,
outs = trackerList.map(_.io.inner.release),
allocs = trackerList.map(_.io.alloc.irel))
io.outer.release.bits.data := io.inner.release.bits.data
io.outer.release.bits.data := irel.bits.data
when (io.orel().hasData()) {
io.outer.release.bits.addr_beat := io.inner.release.bits.addr_beat
io.outer.release.bits.addr_beat := irel.bits.addr_beat
}
// Wire probe requests and grant reply to clients, finish acks from clients