From 06ed9c57942a50def79a20b01b49ad58263e1c44 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Tue, 5 Jul 2016 10:18:25 -0700 Subject: [PATCH] add a single-entry queue in front of acquire and release for bufferless broadcast hub --- uncore/src/main/scala/agents/Bufferless.scala | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/uncore/src/main/scala/agents/Bufferless.scala b/uncore/src/main/scala/agents/Bufferless.scala index 93b75785..f0554ceb 100644 --- a/uncore/src/main/scala/agents/Bufferless.scala +++ b/uncore/src/main/scala/agents/Bufferless.scala @@ -36,24 +36,26 @@ class BufferlessBroadcastHub(implicit p: Parameters) extends HierarchicalCoheren io.inner.release.valid && io.irel().conflicts(io.iacq()) + val iacq = Queue(io.inner.acquire, 1, pipe=true) doInputRoutingWithAllocation( - in = io.inner.acquire, + in = iacq, outs = trackerList.map(_.io.inner.acquire), allocs = trackerList.map(_.io.alloc.iacq), allocOverride = Some(!irel_vs_iacq_conflict)) - io.outer.acquire.bits.data := io.inner.acquire.bits.data + io.outer.acquire.bits.data := iacq.bits.data when (io.oacq().hasData()) { - io.outer.acquire.bits.addr_beat := io.inner.acquire.bits.addr_beat + io.outer.acquire.bits.addr_beat := iacq.bits.addr_beat } // Handle releases, which might be voluntary and might have data + val irel = Queue(io.inner.release, 1, pipe=true) doInputRoutingWithAllocation( - in = io.inner.release, + in = irel, outs = trackerList.map(_.io.inner.release), allocs = trackerList.map(_.io.alloc.irel)) - io.outer.release.bits.data := io.inner.release.bits.data + io.outer.release.bits.data := irel.bits.data when (io.orel().hasData()) { - io.outer.release.bits.addr_beat := io.inner.release.bits.addr_beat + io.outer.release.bits.addr_beat := irel.bits.addr_beat } // Wire probe requests and grant reply to clients, finish acks from clients