riscv/rocket-chip
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Shave a gate delay off I$ backpressure path

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The deleted code was a holdover from Hwacha's vector fences.
This commit is contained in:
Andrew Waterman 2017-08-04 00:40:18 -07:00
parent ecc2ee366c
commit 06a831310b
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/RocketCore.scala
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@ -596,7 +596,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
io.imem.sfence.bits.asid := wb_reg_rs2 io.imem.sfence.bits.asid := wb_reg_rs2
io.ptw.sfence := io.imem.sfence io.ptw.sfence := io.imem.sfence
ibuf.io.inst(0).ready := !ctrl_stalld || csr.io.interrupt ibuf.io.inst(0).ready := !ctrl_stalld
io.imem.btb_update.valid := (mem_reg_replay && mem_reg_btb_hit) || (mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi || mem_cfi_taken)) io.imem.btb_update.valid := (mem_reg_replay && mem_reg_btb_hit) || (mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi || mem_cfi_taken))
io.imem.btb_update.bits.isValid := !mem_reg_replay && mem_cfi io.imem.btb_update.bits.isValid := !mem_reg_replay && mem_cfi