riscv/rocket-chip
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Don't report I$ fetch faults on TLB misses!

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This commit is contained in:
Andrew Waterman 2016-10-04 14:36:58 -07:00
parent 516481b68b
commit 064c9ebdc6
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/frontend.scala
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@ -77,7 +77,7 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
s2_pc := s1_pc s2_pc := s1_pc
s2_speculative := s1_speculative s2_speculative := s1_speculative
s2_cacheable := tlb.io.resp.cacheable s2_cacheable := tlb.io.resp.cacheable
s2_xcpt_if := tlb.io.resp.xcpt_if s2_xcpt_if := tlb.io.resp.xcpt_if && !tlb.io.resp.miss
} }
} }
when (io.cpu.req.valid) { when (io.cpu.req.valid) {