riscv/rocket-chip
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make sure Memtest generators write different data to each address

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This commit is contained in:
Howard Mao 2016-07-29 14:22:46 -07:00
parent 5a3beca097
commit 064020bdd7
1 changed files with 2 additions and 2 deletions
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groundtest/src/main/scala/Generator.scala
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@ -81,7 +81,7 @@ class UncachedTileLinkGenerator(id: Int)
val data_prefix = Cat(UInt(id, log2Up(nGens)), req_cnt) val data_prefix = Cat(UInt(id, log2Up(nGens)), req_cnt)
val word_data = Wire(UInt(width = genWordBits)) val word_data = Wire(UInt(width = genWordBits))
word_data := Cat(data_prefix, full_addr) word_data := Cat(data_prefix, part_of_full_addr)
val beat_data = Fill(tlDataBits / genWordBits, word_data) val beat_data = Fill(tlDataBits / genWordBits, word_data)
val wshift = Cat(beatOffset(full_addr), UInt(0, wordOffset)) val wshift = Cat(beatOffset(full_addr), UInt(0, wordOffset))
val wmask = Fill(genWordBits / 8, Bits(1, 1)) << wshift val wmask = Fill(genWordBits / 8, Bits(1, 1)) << wshift
@ -151,7 +151,7 @@ class HellaCacheGenerator(id: Int)
UInt(0, wordOffset) UInt(0, wordOffset)
} }
val req_addr = UInt(startAddress) + Cat(req_cnt, part_of_req_addr) val req_addr = UInt(startAddress) + Cat(req_cnt, part_of_req_addr)
val req_data = Cat(UInt(id, log2Up(nGens)), req_addr) val req_data = Cat(UInt(id, log2Up(nGens)), req_cnt, part_of_req_addr)
io.mem.req.valid := sending && !io.status.finished io.mem.req.valid := sending && !io.status.finished
io.mem.req.bits.addr := req_addr io.mem.req.bits.addr := req_addr