riscv/rocket-chip
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TLBuffer: replace TLBufferChain with TLBuffer.chain

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This commit is contained in:
Wesley W. Terpstra
2017-10-25 16:30:07 -07:00
parent ce2b904b19
commit 05d48d1807
4 changed files with 8 additions and 42 deletions
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12
src/main/scala/coreplex/FrontBus.scala
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@ -28,16 +28,12 @@ class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrap
master_fixer.node :=* master_buffer.node
inwardNode :=* master_fixer.node
def fromSyncPorts(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
val (in, out) = bufferChain(addBuffers, name)
master_buffer.node :=* out
in
def fromSyncPorts(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = SourceCardinality { implicit p =>
TLBuffer.chain(addBuffers).foldLeft(master_buffer.node:TLInwardNode)(_ :=? _)
}
def fromSyncMasters(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
val (in, out) = bufferChain(addBuffers, name)
master_buffer.node :=* out
in
def fromSyncMasters(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = SourceCardinality { implicit p =>
TLBuffer.chain(addBuffers).foldLeft(master_buffer.node:TLInwardNode)(_ :=? _)
}
def fromCoherentChip: TLInwardNode = inwardNode

4
src/main/scala/coreplex/SystemBus.scala
View File

@ -39,9 +39,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
def toSplitSlaves: TLOutwardNode = outwardSplitNode
def toPeripheryBus(addBuffers: Int = 0): TLOutwardNode = {
val (in, out) = bufferChain(addBuffers, name = Some("pbus"))
in := pbus_fixer.node
out
TLBuffer.chain(addBuffers).foldRight(pbus_fixer.node:TLOutwardNode)(_ := _)
}
val toMemoryBus: TLOutwardNode = outwardNode