From 05d48d1807a8fe4a8073f21f796b53303c62ef78 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Wed, 25 Oct 2017 16:30:07 -0700
Subject: [PATCH] TLBuffer: replace TLBufferChain with TLBuffer.chain

---
 src/main/scala/coreplex/FrontBus.scala  | 12 ++++--------
 src/main/scala/coreplex/SystemBus.scala |  4 +---
 src/main/scala/tilelink/Buffer.scala    | 18 ------------------
 src/main/scala/tilelink/Bus.scala       | 16 +++-------------
 4 files changed, 8 insertions(+), 42 deletions(-)

diff --git a/src/main/scala/coreplex/FrontBus.scala b/src/main/scala/coreplex/FrontBus.scala
index 2ece4503..ce3e95f9 100644
--- a/src/main/scala/coreplex/FrontBus.scala
+++ b/src/main/scala/coreplex/FrontBus.scala
@@ -28,16 +28,12 @@ class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrap
   master_fixer.node :=* master_buffer.node
   inwardNode :=* master_fixer.node
 
-  def fromSyncPorts(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
-    val (in, out) = bufferChain(addBuffers, name)
-    master_buffer.node :=* out
-    in
+  def fromSyncPorts(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = SourceCardinality { implicit p =>
+    TLBuffer.chain(addBuffers).foldLeft(master_buffer.node:TLInwardNode)(_ :=? _)
   }
 
-  def fromSyncMasters(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
-    val (in, out) = bufferChain(addBuffers, name)
-    master_buffer.node :=* out
-    in
+  def fromSyncMasters(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = SourceCardinality { implicit p =>
+    TLBuffer.chain(addBuffers).foldLeft(master_buffer.node:TLInwardNode)(_ :=? _)
   }
 
   def fromCoherentChip: TLInwardNode = inwardNode
diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala
index 46820c76..138adc81 100644
--- a/src/main/scala/coreplex/SystemBus.scala
+++ b/src/main/scala/coreplex/SystemBus.scala
@@ -39,9 +39,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
   def toSplitSlaves: TLOutwardNode = outwardSplitNode
 
   def toPeripheryBus(addBuffers: Int = 0): TLOutwardNode = {
-    val (in, out) = bufferChain(addBuffers, name = Some("pbus"))
-    in := pbus_fixer.node
-    out
+    TLBuffer.chain(addBuffers).foldRight(pbus_fixer.node:TLOutwardNode)(_ := _)
   }
 
   val toMemoryBus: TLOutwardNode = outwardNode
diff --git a/src/main/scala/tilelink/Buffer.scala b/src/main/scala/tilelink/Buffer.scala
index 6026bde1..63c142c0 100644
--- a/src/main/scala/tilelink/Buffer.scala
+++ b/src/main/scala/tilelink/Buffer.scala
@@ -78,21 +78,3 @@ object TLBuffer
     buffers.map(_.node)
   }
 }
-
-class TLBufferChain(depth: Int)(implicit p: Parameters) extends SimpleLazyModule {
-  val buf_chain = List.fill(depth)(LazyModule(new TLBuffer(BufferParams.default)))
-  val node = buf_chain.map(_.node:TLNode).reduceOption(_ :=? _).getOrElse(TLIdentityNode())
-}
-
-object TLBufferChain
-{
-  def apply(depth: Int)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
-    if (depth > 0) {
-      val buffer = LazyModule(new TLBufferChain(depth))
-      buffer.node :=? x
-      buffer.node
-    } else {
-      x
-    }
-  }
-}
diff --git a/src/main/scala/tilelink/Bus.scala b/src/main/scala/tilelink/Bus.scala
index 5f2d018b..b078358b 100644
--- a/src/main/scala/tilelink/Bus.scala
+++ b/src/main/scala/tilelink/Bus.scala
@@ -68,34 +68,24 @@ abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p
   protected def inwardNode: TLInwardNode = xbar.node
   protected def inwardBufNode: TLInwardNode = master_buffer.node
 
-  protected def bufferChain(depth: Int, name: Option[String] = None): (TLInwardNode, TLOutwardNode) = {
-    SourceCardinality { implicit p =>
-      val chain = LazyModule(new TLBufferChain(depth))
-      name.foreach { n => chain.suggestName(s"${busName}_${n}_TLBufferChain")}
-      (chain.node, chain.node)
-    }
-  }
-
   def bufferFromMasters: TLInwardNode = inwardBufNode
 
   def bufferToSlaves: TLOutwardNode = outwardBufNode 
 
   def toSyncSlaves(name: Option[String] = None, addBuffers: Int = 0): TLOutwardNode = SinkCardinality { implicit p =>
-    TLBufferChain(addBuffers)(outwardBufNode)
+    TLBuffer.chain(addBuffers).foldRight(outwardBufNode)(_ :=? _)
   }
 
   def toAsyncSlaves(sync: Int = 3, name: Option[String] = None, addBuffers: Int = 0): TLAsyncOutwardNode = SinkCardinality { implicit p =>
     val source = LazyModule(new TLAsyncCrossingSource(sync))
     name.foreach{ n => source.suggestName(s"${busName}_${n}_TLAsyncCrossingSource")}
-    source.node :=? TLBufferChain(addBuffers)(outwardNode)
-    source.node
+    source.node :=? TLBuffer.chain(addBuffers).foldRight(outwardNode)(_ :=? _)
   }
 
   def toRationalSlaves(name: Option[String] = None, addBuffers: Int = 0): TLRationalOutwardNode = SinkCardinality { implicit p =>
     val source = LazyModule(new TLRationalCrossingSource())
     name.foreach{ n => source.suggestName(s"${busName}_${n}_TLRationalCrossingSource")}
-    source.node :=? TLBufferChain(addBuffers)(outwardNode)
-    source.node
+    source.node :=? TLBuffer.chain(addBuffers).foldRight(outwardNode)(_ :=? _)
   }
 
   def toVariableWidthSlaves: TLOutwardNode = outwardFragNode