riscv/rocket-chip
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Work around zero-entry vec issue in Chisel

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This commit is contained in:
Andrew Waterman 2017-03-27 17:53:48 -07:00
parent ab300f7985
commit 05cbdced78
2 changed files with 2 additions and 2 deletions
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2
src/main/scala/rocket/CSR.scala
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@ -697,7 +697,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
}
}
reg_mip.lip zip io.interrupts.lip foreach { case (r, i) => r := i }
reg_mip.lip := (io.interrupts.lip: Seq[Bool])
reg_mip.mtip := io.interrupts.mtip
reg_mip.msip := io.interrupts.msip
reg_mip.meip := io.interrupts.meip

2
src/main/scala/rocket/TLB.scala
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@ -99,7 +99,7 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
val pmp = Module(new PMPChecker(lgMaxSize))
pmp.io.addr := mpu_physaddr
pmp.io.size := io.req.bits.size
pmp.io.pmp := io.ptw.pmp
pmp.io.pmp := (io.ptw.pmp: Seq[PMP])
pmp.io.prv := Mux(Bool(usingVM) && (do_refill || io.req.bits.passthrough /* PTW */), PRV.S, priv)
val legal_address = edge.manager.findSafe(mpu_physaddr).reduce(_||_)
def fastCheck(member: TLManagerParameters => Boolean) =