From 05cbdced78d66be7e8f2491c04641113f008b0c8 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 27 Mar 2017 17:53:48 -0700 Subject: [PATCH] Work around zero-entry vec issue in Chisel --- src/main/scala/rocket/CSR.scala | 2 +- src/main/scala/rocket/TLB.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala index 4b85aa44..5ff0626a 100644 --- a/src/main/scala/rocket/CSR.scala +++ b/src/main/scala/rocket/CSR.scala @@ -697,7 +697,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param } } - reg_mip.lip zip io.interrupts.lip foreach { case (r, i) => r := i } + reg_mip.lip := (io.interrupts.lip: Seq[Bool]) reg_mip.mtip := io.interrupts.mtip reg_mip.msip := io.interrupts.msip reg_mip.meip := io.interrupts.meip diff --git a/src/main/scala/rocket/TLB.scala b/src/main/scala/rocket/TLB.scala index b2714a35..de3a90d1 100644 --- a/src/main/scala/rocket/TLB.scala +++ b/src/main/scala/rocket/TLB.scala @@ -99,7 +99,7 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters val pmp = Module(new PMPChecker(lgMaxSize)) pmp.io.addr := mpu_physaddr pmp.io.size := io.req.bits.size - pmp.io.pmp := io.ptw.pmp + pmp.io.pmp := (io.ptw.pmp: Seq[PMP]) pmp.io.prv := Mux(Bool(usingVM) && (do_refill || io.req.bits.passthrough /* PTW */), PRV.S, priv) val legal_address = edge.manager.findSafe(mpu_physaddr).reduce(_||_) def fastCheck(member: TLManagerParameters => Boolean) =