riscv/rocket-chip
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tilelink2: specify the minLatency for SRAM+RR

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Wesley W. Terpstra committed 2016-09-22 15:18:54 -07:00
1 parent 44277c1db3
commit 05beb20dc4
5 files changed
+15 -12
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src/main/scala/uncore/tilelink2/SRAM.scala
+2 -1
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@@ -13,7 +13,8 @@ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0))) // requests are handled in order
fifoId = Some(0)), // requests are handled in order
minLatency = 1) // no bypass needed for this device
// We require the address range to include an entire beat (for the write mask)
require ((address.mask & (beatBytes-1)) == beatBytes-1)