From 05beb20dc439e336ab535d90fcd09d36ad9b63b1 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 21 Sep 2016 17:38:32 -0700 Subject: [PATCH] tilelink2: specify the minLatency for SRAM+RR --- src/main/scala/uncore/devices/Prci.scala | 2 +- src/main/scala/uncore/tilelink2/RegMapper.scala | 6 +++--- src/main/scala/uncore/tilelink2/RegisterRouter.scala | 12 +++++++----- .../scala/uncore/tilelink2/RegisterRouterTest.scala | 4 ++-- src/main/scala/uncore/tilelink2/SRAM.scala | 3 ++- 5 files changed, 15 insertions(+), 12 deletions(-) diff --git a/src/main/scala/uncore/devices/Prci.scala b/src/main/scala/uncore/devices/Prci.scala index 1024aae2..ce32e8c2 100644 --- a/src/main/scala/uncore/devices/Prci.scala +++ b/src/main/scala/uncore/devices/Prci.scala @@ -89,7 +89,7 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep /** Power, Reset, Clock, Interrupt */ // Magic TL2 Incantation to create a TL2 Slave class CoreplexLocalInterrupter(c: CoreplexLocalInterrupterConfig)(implicit val p: Parameters) - extends TLRegisterRouter(c.address, 0, c.size, None, c.beatBytes, false)( + extends TLRegisterRouter(c.address, 0, c.size, 0, c.beatBytes, false)( new TLRegBundle((c, p), _) with CoreplexLocalInterrupterBundle)( new TLRegModule((c, p), _, _) with CoreplexLocalInterrupterModule) { diff --git a/src/main/scala/uncore/tilelink2/RegMapper.scala b/src/main/scala/uncore/tilelink2/RegMapper.scala index 6678e500..5a661af8 100644 --- a/src/main/scala/uncore/tilelink2/RegMapper.scala +++ b/src/main/scala/uncore/tilelink2/RegMapper.scala @@ -28,7 +28,7 @@ class RegMapperOutput(params: RegMapperParams) extends GenericParameterizedBundl object RegMapper { // Create a generic register-based device - def apply(bytes: Int, concurrency: Option[Int], undefZero: Boolean, in: DecoupledIO[RegMapperInput], mapping: RegField.Map*) = { + def apply(bytes: Int, concurrency: Int, undefZero: Boolean, in: DecoupledIO[RegMapperInput], mapping: RegField.Map*) = { val regmap = mapping.toList.filter(!_._2.isEmpty) require (!regmap.isEmpty) @@ -49,9 +49,9 @@ object RegMapper // Must this device pipeline the control channel? val pipelined = regmap.map(_._2.map(_.pipelined)).flatten.reduce(_ || _) - val depth = concurrency.getOrElse(if (pipelined) 1 else 0) + val depth = concurrency require (depth >= 0) - require (!pipelined || depth > 0) + require (!pipelined || depth > 0, "Register-based device with request/response handshaking needs concurrency > 0") val back = if (depth > 0) Queue(front, depth, pipe = depth == 1) else front // Convert to and from Bits diff --git a/src/main/scala/uncore/tilelink2/RegisterRouter.scala b/src/main/scala/uncore/tilelink2/RegisterRouter.scala index 7b6bdc21..44802259 100644 --- a/src/main/scala/uncore/tilelink2/RegisterRouter.scala +++ b/src/main/scala/uncore/tilelink2/RegisterRouter.scala @@ -3,14 +3,16 @@ package uncore.tilelink2 import Chisel._ +import scala.math.max -class TLRegisterNode(address: AddressSet, concurrency: Option[Int] = None, beatBytes: Int = 4, undefZero: Boolean = true) +class TLRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true) extends TLManagerNode(beatBytes, TLManagerParameters( address = Seq(address), supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), - fifoId = Some(0))) // requests are handled in order + fifoId = Some(0)), // requests are handled in order + minLatency = max(concurrency, 1)) // the Queue adds at least one cycle { require (address.contiguous) @@ -64,7 +66,7 @@ class TLRegisterNode(address: AddressSet, concurrency: Option[Int] = None, beatB object TLRegisterNode { - def apply(address: AddressSet, concurrency: Option[Int] = None, beatBytes: Int = 4, undefZero: Boolean = true) = + def apply(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true) = new TLRegisterNode(address, concurrency, beatBytes, undefZero) } @@ -72,7 +74,7 @@ object TLRegisterNode // register mapped device from a totally abstract register mapped device. // See GPIO.scala in this directory for an example -abstract class TLRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Option[Int], beatBytes: Int, undefZero: Boolean) extends LazyModule +abstract class TLRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean) extends LazyModule { val node = TLRegisterNode(address, concurrency, beatBytes, undefZero) val intnode = IntSourceNode(interrupts) @@ -97,7 +99,7 @@ class TLRegModule[P, B <: TLRegBundleBase](val params: P, bundleBuilder: => B, r } class TLRegisterRouter[B <: TLRegBundleBase, M <: LazyModuleImp] - (val base: BigInt, val interrupts: Int = 0, val size: BigInt = 4096, val concurrency: Option[Int] = None, val beatBytes: Int = 4, undefZero: Boolean = true) + (val base: BigInt, val interrupts: Int = 0, val size: BigInt = 4096, val concurrency: Int = 0, val beatBytes: Int = 4, undefZero: Boolean = true) (bundleBuilder: TLRegBundleArg => B) (moduleBuilder: (=> B, TLRegisterRouterBase) => M) extends TLRegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes, undefZero) diff --git a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala index eb6a1944..395bae81 100644 --- a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala +++ b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala @@ -216,7 +216,7 @@ trait RRTest0Module extends HasRegMap regmap(RRTest0Map.map:_*) } -class RRTest0(address: BigInt) extends TLRegisterRouter(address, 0, 32, Some(0), 4)( +class RRTest0(address: BigInt) extends TLRegisterRouter(address, 0, 32, 0, 4)( new TLRegBundle((), _) with RRTest0Bundle)( new TLRegModule((), _, _) with RRTest0Module) @@ -255,6 +255,6 @@ trait RRTest1Module extends Module with HasRegMap regmap(map:_*) } -class RRTest1(address: BigInt) extends TLRegisterRouter(address, 0, 32, Some(6), 4)( +class RRTest1(address: BigInt) extends TLRegisterRouter(address, 0, 32, 6, 4)( new TLRegBundle((), _) with RRTest1Bundle)( new TLRegModule((), _, _) with RRTest1Module) diff --git a/src/main/scala/uncore/tilelink2/SRAM.scala b/src/main/scala/uncore/tilelink2/SRAM.scala index 84a775f2..9b5b3d8a 100644 --- a/src/main/scala/uncore/tilelink2/SRAM.scala +++ b/src/main/scala/uncore/tilelink2/SRAM.scala @@ -13,7 +13,8 @@ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4) supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), - fifoId = Some(0))) // requests are handled in order + fifoId = Some(0)), // requests are handled in order + minLatency = 1) // no bypass needed for this device // We require the address range to include an entire beat (for the write mask) require ((address.mask & (beatBytes-1)) == beatBytes-1)