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tilelink2: specify the minLatency for SRAM+RR

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This commit is contained in:
Wesley W. Terpstra
2016-09-21 17:38:32 -07:00
parent 44277c1db3
commit 05beb20dc4
5 changed files with 15 additions and 12 deletions
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4
src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
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@ -216,7 +216,7 @@ trait RRTest0Module extends HasRegMap
regmap(RRTest0Map.map:_*)
}
class RRTest0(address: BigInt) extends TLRegisterRouter(address, 0, 32, Some(0), 4)(
class RRTest0(address: BigInt) extends TLRegisterRouter(address, 0, 32, 0, 4)(
new TLRegBundle((), _) with RRTest0Bundle)(
new TLRegModule((), _, _) with RRTest0Module)
@ -255,6 +255,6 @@ trait RRTest1Module extends Module with HasRegMap
regmap(map:_*)
}
class RRTest1(address: BigInt) extends TLRegisterRouter(address, 0, 32, Some(6), 4)(
class RRTest1(address: BigInt) extends TLRegisterRouter(address, 0, 32, 6, 4)(
new TLRegBundle((), _) with RRTest1Bundle)(
new TLRegModule((), _, _) with RRTest1Module)