tilelink2: specify the minLatency for SRAM+RR
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@ -3,14 +3,16 @@
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package uncore.tilelink2
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import Chisel._
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import scala.math.max
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class TLRegisterNode(address: AddressSet, concurrency: Option[Int] = None, beatBytes: Int = 4, undefZero: Boolean = true)
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class TLRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true)
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extends TLManagerNode(beatBytes, TLManagerParameters(
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address = Seq(address),
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supportsGet = TransferSizes(1, beatBytes),
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supportsPutPartial = TransferSizes(1, beatBytes),
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supportsPutFull = TransferSizes(1, beatBytes),
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fifoId = Some(0))) // requests are handled in order
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fifoId = Some(0)), // requests are handled in order
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minLatency = max(concurrency, 1)) // the Queue adds at least one cycle
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{
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require (address.contiguous)
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@ -64,7 +66,7 @@ class TLRegisterNode(address: AddressSet, concurrency: Option[Int] = None, beatB
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object TLRegisterNode
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{
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def apply(address: AddressSet, concurrency: Option[Int] = None, beatBytes: Int = 4, undefZero: Boolean = true) =
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def apply(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true) =
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new TLRegisterNode(address, concurrency, beatBytes, undefZero)
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}
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@ -72,7 +74,7 @@ object TLRegisterNode
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// register mapped device from a totally abstract register mapped device.
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// See GPIO.scala in this directory for an example
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abstract class TLRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Option[Int], beatBytes: Int, undefZero: Boolean) extends LazyModule
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abstract class TLRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean) extends LazyModule
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{
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val node = TLRegisterNode(address, concurrency, beatBytes, undefZero)
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val intnode = IntSourceNode(interrupts)
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@ -97,7 +99,7 @@ class TLRegModule[P, B <: TLRegBundleBase](val params: P, bundleBuilder: => B, r
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}
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class TLRegisterRouter[B <: TLRegBundleBase, M <: LazyModuleImp]
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(val base: BigInt, val interrupts: Int = 0, val size: BigInt = 4096, val concurrency: Option[Int] = None, val beatBytes: Int = 4, undefZero: Boolean = true)
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(val base: BigInt, val interrupts: Int = 0, val size: BigInt = 4096, val concurrency: Int = 0, val beatBytes: Int = 4, undefZero: Boolean = true)
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(bundleBuilder: TLRegBundleArg => B)
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(moduleBuilder: (=> B, TLRegisterRouterBase) => M)
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extends TLRegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes, undefZero)
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