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tilelink2: specify the minLatency for SRAM+RR

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Wesley W. Terpstra
2016-09-21 17:38:32 -07:00
parent 44277c1db3
commit 05beb20dc4
5 changed files with 15 additions and 12 deletions
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2
src/main/scala/uncore/devices/Prci.scala
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@ -89,7 +89,7 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep
/** Power, Reset, Clock, Interrupt */
// Magic TL2 Incantation to create a TL2 Slave
class CoreplexLocalInterrupter(c: CoreplexLocalInterrupterConfig)(implicit val p: Parameters)
extends TLRegisterRouter(c.address, 0, c.size, None, c.beatBytes, false)(
extends TLRegisterRouter(c.address, 0, c.size, 0, c.beatBytes, false)(
new TLRegBundle((c, p), _) with CoreplexLocalInterrupterBundle)(
new TLRegModule((c, p), _, _) with CoreplexLocalInterrupterModule)
{