riscv/rocket-chip
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cleanup mergeData and prep for cleaner data_buffer in L2

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Henry Cook committed 2015-03-11 15:43:41 -07:00
1 parent b4ed1d9121
commit 059575c334
2 files changed
+37 -37
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uncore/src/main/scala/uncore.scala
+2
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@@ -21,6 +21,8 @@ trait CoherenceAgentParameters extends UsesParameters {
def outerTLParams = params.alterPartial({ case TLId => params(OuterTLId)})
val outerDataBeats = outerTLParams(TLDataBeats)
val outerDataBits = outerTLParams(TLDataBits)
val outerBeatAddrBits = log2Up(outerDataBeats)
val outerByteAddrBits = log2Up(outerDataBits/8)
def innerTLParams = params.alterPartial({case TLId => params(InnerTLId)})
val innerDataBeats = innerTLParams(TLDataBeats)
val innerDataBits = innerTLParams(TLDataBits)