riscv/rocket-chip
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For D$, use source 0 through N-1 for MMIO, not 1 through N

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This makes the code a bit cleaner.
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Andrew Waterman
2017-03-23 13:07:14 -07:00
parent 3951e57789
commit 0538dc77ce
2 changed files with 7 additions and 9 deletions
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src/main/scala/rocket/HellaCache.scala
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@ -60,7 +60,6 @@ trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParamet
def encRowBits = encDataBits*rowWords
def lrscCycles = 32 // ISA requires 16-insn LRSC sequences to succeed
def nIOMSHRs = cacheParams.nMMIOs
def maxUncachedInFlight = cacheParams.nMMIOs
def dataScratchpadSize = cacheParams.dataScratchpadBytes
require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)")