268 lines
8.6 KiB
Scala
268 lines
8.6 KiB
Scala
// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package rocket
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import Chisel._
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import config.{Parameters, Field}
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import coreplex._
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import diplomacy._
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import tile._
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import uncore.constants._
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import uncore.tilelink2._
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import uncore.util.Code
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import util.{ParameterizedBundle, RandomReplacement}
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import scala.collection.mutable.ListBuffer
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import scala.math.max
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case class DCacheParams(
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nSets: Int = 64,
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nWays: Int = 4,
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rowBits: Int = 64,
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nTLBEntries: Int = 32,
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splitMetadata: Boolean = false,
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ecc: Option[Code] = None,
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nMSHRs: Int = 1,
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nSDQ: Int = 17,
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nRPQ: Int = 16,
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nMMIOs: Int = 1,
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blockBytes: Int = 64,
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scratch: Option[BigInt] = None) extends L1CacheParams {
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def dataScratchpadBytes: Int = scratch.map(_ => nSets*blockBytes).getOrElse(0)
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def replacement = new RandomReplacement(nWays)
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require((!scratch.isDefined || nWays == 1),
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"Scratchpad only allowed in direct-mapped cache.")
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require((!scratch.isDefined || nMSHRs == 0),
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"Scratchpad only allowed in blocking cache.")
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require(isPow2(nSets), s"nSets($nSets) must be pow2")
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}
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trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters {
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val cacheParams = tileParams.dcache.get
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val cfg = cacheParams
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def wordBits = xLen // really, xLen max
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def wordBytes = wordBits/8
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def wordOffBits = log2Up(wordBytes)
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def beatBytes = cacheBlockBytes / cacheDataBeats
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def beatWords = beatBytes / wordBytes
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def beatOffBits = log2Up(beatBytes)
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def idxMSB = untagBits-1
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def idxLSB = blockOffBits
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def offsetmsb = idxLSB-1
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def offsetlsb = wordOffBits
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def rowWords = rowBits/wordBits
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def doNarrowRead = coreDataBits * nWays % rowBits == 0
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def encDataBits = code.width(coreDataBits)
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def encRowBits = encDataBits*rowWords
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def lrscCycles = 32 // ISA requires 16-insn LRSC sequences to succeed
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def nIOMSHRs = cacheParams.nMMIOs
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def dataScratchpadSize = cacheParams.dataScratchpadBytes
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require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)")
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// TODO should rowBits even be seperably specifiable?
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require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)")
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// would need offset addr for puts if data width < xlen
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require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)")
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require(!usingVM || untagBits <= pgIdxBits, s"untagBits($untagBits) > pgIdxBits($pgIdxBits)")
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}
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abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module
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with HasL1HellaCacheParameters
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abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasL1HellaCacheParameters
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/** Bundle definitions for HellaCache interfaces */
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trait HasCoreMemOp extends HasCoreParameters {
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val addr = UInt(width = coreMaxAddrBits)
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val tag = Bits(width = dcacheReqTagBits)
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val cmd = Bits(width = M_SZ)
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val typ = Bits(width = MT_SZ)
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}
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trait HasCoreData extends HasCoreParameters {
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val data = Bits(width = coreDataBits)
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}
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class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp {
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val phys = Bool()
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}
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class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData
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class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p)
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with HasCoreMemOp
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with HasCoreData {
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val replay = Bool()
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val has_data = Bool()
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val data_word_bypass = Bits(width = coreDataBits)
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val store_data = Bits(width = coreDataBits)
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}
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class AlignmentExceptions extends Bundle {
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val ld = Bool()
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val st = Bool()
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}
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class HellaCacheExceptions extends Bundle {
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val ma = new AlignmentExceptions
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val pf = new AlignmentExceptions
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}
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// interface between D$ and processor/DTLB
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class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) {
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val req = Decoupled(new HellaCacheReq)
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val s1_kill = Bool(OUTPUT) // kill previous cycle's req
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val s1_data = Bits(OUTPUT, coreDataBits) // data for previous cycle's req
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val s2_nack = Bool(INPUT) // req from two cycles ago is rejected
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// performance events
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val acquire = Bool(INPUT)
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val release = Bool(INPUT)
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val resp = Valid(new HellaCacheResp).flip
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val replay_next = Bool(INPUT)
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val xcpt = (new HellaCacheExceptions).asInput
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val invalidate_lr = Bool(OUTPUT)
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val ordered = Bool(INPUT)
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}
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/** Base classes for Diplomatic TL2 HellaCaches */
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abstract class HellaCache(implicit p: Parameters) extends LazyModule {
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private val cfg = p(TileKey).dcache.get
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val firstMMIO = max(1, cfg.nMSHRs)
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val node = TLClientNode(Seq(TLClientPortParameters(
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clients = cfg.scratch.map { _ => Seq(
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TLClientParameters(
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sourceId = IdRange(0, cfg.nMMIOs),
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requestFifo = true))
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} getOrElse { Seq(
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TLClientParameters(
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sourceId = IdRange(0, firstMMIO),
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supportsProbe = TransferSizes(1, cfg.blockBytes)),
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TLClientParameters(
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sourceId = IdRange(firstMMIO, firstMMIO+cfg.nMMIOs),
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requestFifo = true))
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},
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minLatency = 1)))
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val module: HellaCacheModule
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}
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class HellaCacheBundle(outer: HellaCache) extends Bundle {
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implicit val p = outer.p
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val cpu = (new HellaCacheIO).flip
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val ptw = new TLBPTWIO()
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val mem = outer.node.bundleOut
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}
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class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
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with HasL1HellaCacheParameters {
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implicit val edge = outer.node.edgesOut(0)
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val io = new HellaCacheBundle(outer)
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val tl_out = io.mem(0)
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// IOMSHRs must be FIFO
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edge.manager.requireFifo()
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}
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object HellaCache {
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def apply(blocking: Boolean, scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) = {
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if (blocking) LazyModule(new DCache(scratch))
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else LazyModule(new NonBlockingDCache)
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}
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}
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/** Mix-ins for constructing tiles that have a HellaCache */
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trait HasHellaCache extends HasTileLinkMasterPort {
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val module: HasHellaCacheModule
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implicit val p: Parameters
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def findScratchpadFromICache: Option[AddressSet]
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var nDCachePorts = 0
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val dcache = HellaCache(tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _)
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masterNode := dcache.node
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}
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trait HasHellaCacheBundle extends HasTileLinkMasterPortBundle {
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val outer: HasHellaCache
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}
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trait HasHellaCacheModule extends HasTileLinkMasterPortModule {
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val outer: HasHellaCache
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//val io: HasHellaCacheBundle
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val dcachePorts = ListBuffer[HellaCacheIO]()
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val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p))
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outer.dcache.module.io.cpu <> dcacheArb.io.mem
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}
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/** Metadata array used for all HellaCaches */
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class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
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val coh = new ClientMetadata
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val tag = UInt(width = tagBits)
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}
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object L1Metadata {
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def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = {
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val meta = Wire(new L1Metadata)
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meta.tag := tag
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meta.coh := coh
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meta
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}
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}
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class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
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val idx = UInt(width = idxBits)
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val way_en = UInt(width = nWays)
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val tag = UInt(width = tagBits)
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}
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class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) {
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val data = new L1Metadata
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}
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class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val rstVal = onReset()
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val io = new Bundle {
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val read = Decoupled(new L1MetaReadReq).flip
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val write = Decoupled(new L1MetaWriteReq).flip
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val resp = Vec(nWays, rstVal.cloneType).asOutput
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}
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val rst_cnt = Reg(init=UInt(0, log2Up(nSets+1)))
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val rst = rst_cnt < UInt(nSets)
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val waddr = Mux(rst, rst_cnt, io.write.bits.idx)
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val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt
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val wmask = Mux(rst || Bool(nWays == 1), SInt(-1), io.write.bits.way_en.asSInt).toBools
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val rmask = Mux(rst || Bool(nWays == 1), SInt(-1), io.read.bits.way_en.asSInt).toBools
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when (rst) { rst_cnt := rst_cnt+UInt(1) }
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val metabits = rstVal.getWidth
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if (hasSplitMetadata) {
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val tag_arrs = List.fill(nWays){ SeqMem(nSets, UInt(width = metabits)) }
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val tag_readout = Wire(Vec(nWays,rstVal.cloneType))
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(0 until nWays).foreach { (i) =>
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when (rst || (io.write.valid && wmask(i))) {
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tag_arrs(i).write(waddr, wdata)
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}
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io.resp(i) := rstVal.fromBits(tag_arrs(i).read(io.read.bits.idx, io.read.valid && rmask(i)))
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}
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} else {
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val tag_arr = SeqMem(nSets, Vec(nWays, UInt(width = metabits)))
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when (rst || io.write.valid) {
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tag_arr.write(waddr, Vec.fill(nWays)(wdata), wmask)
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}
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io.resp := tag_arr.read(io.read.bits.idx, io.read.valid).map(rstVal.fromBits(_))
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}
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io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM
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io.write.ready := !rst
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}
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