riscv/rocket-chip
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Compiles and elaborates, does not pass asm tests

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This commit is contained in:
Henry Cook
2014-10-15 11:46:35 -07:00
parent 86bdbd6535
commit 044b19dbc1
2 changed files with 63 additions and 61 deletions
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31
uncore/src/main/scala/cache.scala
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@ -130,8 +130,9 @@ class L2MetaReadReq extends MetaReadReq with HasL2Id {
}
class L2MetaWriteReq extends MetaWriteReq[L2Metadata](new L2Metadata)
with HasL2Id
with HasL2Id {
override def clone = new L2MetaWriteReq().asInstanceOf[this.type]
}
class L2MetaResp extends L2HellaCacheBundle
with HasL2Id
with HasL2InternalRequestState
@ -360,7 +361,7 @@ abstract class L2XactTracker(innerId: String, outerId: String) extends L2HellaCa
}
class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, outerId: String) extends L2XactTracker(innerId, outerId) {
val s_idle :: s_meta_read :: s_meta_resp :: s_meta_write :: s_data_write :: s_grant :: s_busy :: Nil = Enum(UInt(), 6)
val s_idle :: s_meta_read :: s_meta_resp :: s_meta_write :: s_data_write :: s_grant :: s_busy :: Nil = Enum(UInt(), 7)
val state = Reg(init=s_idle)
val xact = Reg{ new Release }
val xact_internal = Reg{ new L2MetaResp }
@ -399,7 +400,6 @@ class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, ou
io.meta_write.bits.idx := xact.addr(untagBits-1,blockOffBits)
io.meta_write.bits.way_en := xact_internal.way_en
io.meta_write.bits.data := xact_internal.meta
io.meta_resp.valid := Bool(true)
switch (state) {
is(s_idle) {
@ -450,21 +450,22 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
val state = Reg(init=s_idle)
val xact = Reg{ new Acquire }
val xact_internal = Reg{ new L2MetaResp }
val test = Reg{UInt()}
val init_client_id = Reg(init=UInt(0, width = log2Up(nClients)))
//TODO: Will need id reg for merged release xacts
val release_count = Reg(init = UInt(0, width = log2Up(nClients)))
val pending_probes = Reg(init = co.dir())
val curr_p_id = pending_probes.next()
val pending_probes = Reg(init = co.dir().flush)
val curr_p_id = co.dir().next(pending_probes)
val is_uncached = co.messageIsUncached(xact)
val tag_match = xact_internal.tag_match
val needs_writeback = co.needsWriteback(xact_internal.meta.coh)
val is_hit = co.isHit(xact, xact_internal.meta.coh)
val needs_probes = co.requiresProbes(xact.a_type, xact_internal.meta.coh)
val c_rel_had_data = Reg{Bool()}
val c_rel_was_voluntary = Reg{Bool()}
val c_rel_had_data = Reg(init = Bool(false))
val c_rel_was_voluntary = Reg(init = Bool(false))
val wb_buffer = Reg{xact.data.clone}
io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, c_acq.payload.addr) &&
@ -557,12 +558,14 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
val _is_hit = co.isHit(xact, coh)
val _needs_probes = co.requiresProbes(xact.a_type, coh)
xact_internal := io.meta_resp.bits
test := UInt(0)
when(!_needs_writeback) {
xact_internal.meta.coh := co.masterMetadataOnFlush
// xact_internal.meta.coh := co.masterMetadataOnFlush
test := UInt(12)
}
when(_needs_probes) {
pending_probes := coh.sharers
release_count := coh.sharers.count()
release_count := co.dir().count(coh.sharers)
c_rel_had_data := Bool(false)
c_rel_was_voluntary := Bool(false)
}
@ -579,19 +582,21 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
val skip = io.tile_incoherent(curr_p_id) ||
((curr_p_id === init_client_id) &&
!co.requiresSelfProbe(xact.a_type))
io.inner.probe.valid := !(pending_probes.none() || skip)
io.inner.probe.valid := !(co.dir().none(pending_probes) || skip)
when(io.inner.probe.ready || skip) {
pending_probes.pop(curr_p_id)
co.dir().pop(pending_probes, curr_p_id)
}
when(skip) { release_count := release_count - UInt(1) }
// Handle releases, which may have data being written back
io.inner.release.ready := Bool(true)
when(io.inner.release.valid) {
/*
xact_internal.meta.coh := co.masterMetadataOnRelease(
c_rel.payload,
xact_internal.meta.coh,
c_rel.header.src)
*/
when(co.messageHasData(c_rel.payload)) {
c_rel_had_data := Bool(true)
when(tag_match) {
@ -623,7 +628,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
}
is(s_data_resp_wb) {
when(io.data_resp.valid) {
wb_buffer := io.data_resp.bits
wb_buffer := io.data_resp.bits.data
state := s_outer_write_wb
}
}