riscv/rocket-chip
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refactored vector exception handling interface

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This commit is contained in:
Yunsup Lee
2012-03-13 23:45:10 -07:00
parent b100544b25
commit 040d62f372
8 changed files with 91 additions and 90 deletions
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6
rocket/src/main/scala/dpath_util.scala
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@ -79,7 +79,6 @@ class ioDpathPCR extends Bundle()
val irq_ipi = Bool(OUTPUT);
val vecbank = Bits(8, OUTPUT)
val vecbankcnt = UFix(4, OUTPUT)
val vechold = Bool(OUTPUT)
val vec_appvl = UFix(12, INPUT)
val vec_nxregs = UFix(6, INPUT)
val vec_nfregs = UFix(6, INPUT)
@ -101,7 +100,6 @@ class rocketDpathPCR extends Component
val reg_k1 = Reg() { Bits() };
val reg_ptbr = Reg() { UFix() };
val reg_vecbank = Reg(resetVal = Bits("b1111_1111", 8))
val reg_vechold = Reg() { Bool() }
val reg_error_mode = Reg(resetVal = Bool(false));
val reg_status_vm = Reg(resetVal = Bool(false));
@ -143,8 +141,6 @@ class rocketDpathPCR extends Component
cnt = cnt + reg_vecbank(i)
io.vecbankcnt := cnt(3,0)
io.vechold := reg_vechold
val badvaddr_sign = Mux(io.w.data(VADDR_BITS-1), ~io.w.data(63,VADDR_BITS) === UFix(0), io.w.data(63,VADDR_BITS) != UFix(0))
when (io.badvaddr_wen) {
reg_badvaddr := Cat(badvaddr_sign, io.w.data(VADDR_BITS-1,0)).toUFix;
@ -174,7 +170,6 @@ class rocketDpathPCR extends Component
when (io.eret) {
reg_status_s := reg_status_ps;
reg_status_et := Bool(true);
reg_vechold := Bool(false)
}
when (reg_count === reg_compare) {
@ -212,7 +207,6 @@ class rocketDpathPCR extends Component
when (waddr === PCR_K1) { reg_k1 := wdata; }
when (waddr === PCR_PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
when (waddr === PCR_VECBANK) { reg_vecbank := wdata(7,0) }
when (waddr === PCR_VEC_HOLD) { reg_vechold := reg_status_ev && wdata(0) }
}
rdata := Bits(0, 64)