From 040d62f372a254d3d1bbff05094a3f0bfd53c6a5 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Tue, 13 Mar 2012 23:45:10 -0700 Subject: [PATCH] refactored vector exception handling interface --- rocket/src/main/scala/consts.scala | 7 +- rocket/src/main/scala/cpu.scala | 8 +- rocket/src/main/scala/ctrl.scala | 6 +- rocket/src/main/scala/ctrl_vec.scala | 127 +++++++++++++---------- rocket/src/main/scala/dpath.scala | 4 - rocket/src/main/scala/dpath_util.scala | 6 -- rocket/src/main/scala/dpath_vec.scala | 12 +-- rocket/src/main/scala/instructions.scala | 11 +- 8 files changed, 91 insertions(+), 90 deletions(-) diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index 105b6911..3649e6a0 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -7,7 +7,7 @@ object Constants { val HAVE_RVC = false val HAVE_FPU = true - val HAVE_VEC = true + val HAVE_VEC = false val BR_N = UFix(0, 4); val BR_EQ = UFix(1, 4); @@ -144,11 +144,6 @@ object Constants val PCR_VECBANK = UFix(18, 5); val PCR_VECCFG = UFix(19, 5); - // temporaries for vector, these will go away - val PCR_VEC_BACKUP = UFix(29, 5) - val PCR_VEC_KILL = UFix(30, 5) - val PCR_VEC_HOLD = UFix(31, 5) - // definition of bits in PCR status reg val SR_ET = 0; // enable traps val SR_EF = 1; // enable floating point diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala index 08ef77fa..c2cc4893 100644 --- a/rocket/src/main/scala/cpu.scala +++ b/rocket/src/main/scala/cpu.scala @@ -205,10 +205,10 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal) vu.io.xcpt.exception := ctrl.io.vec_iface.exception ctrl.io.vec_iface.exception_ack_valid := vu.io.xcpt.exception_ack_valid vu.io.xcpt.exception_ack_ready := ctrl.io.vec_iface.exception_ack_ready - vu.io.xcpt.backup := dpath.io.vec_iface.backup - vu.io.xcpt.backup_addr := dpath.io.vec_iface.backup_addr.toUFix - vu.io.xcpt.kill := dpath.io.vec_iface.kill - vu.io.xcpt.hold := dpath.io.vec_iface.hold + vu.io.xcpt.evac := ctrl.io.vec_iface.evac + vu.io.xcpt.evac_addr := dpath.io.vec_iface.evac_addr.toUFix + vu.io.xcpt.kill := ctrl.io.vec_iface.kill + vu.io.xcpt.hold := ctrl.io.vec_iface.hold // hooking up vector memory interface val storegen = new StoreDataGen diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index e9eff28a..d71d8b02 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -306,7 +306,10 @@ object rocketCtrlDecode VENQIMM1-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N), VENQIMM2-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N), VENQCNT-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N), - VWAITXCPT-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,Y)) + VXCPTEVAC-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N), + VXCPTKILL-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N), + VXCPTWAIT-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,Y), + VXCPTHOLD-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N)) } class rocketCtrl extends Component @@ -630,6 +633,7 @@ class rocketCtrl extends Component vec.io.s := io.dpath.status(SR_S) vec.io.sr_ev := io.dpath.status(SR_EV) vec.io.exception := wb_reg_exception + vec.io.eret := wb_reg_eret vec_replay = vec.io.replay vec_stalld = vec.io.stalld // || id_vfence_cv && !vec.io.vfence_ready diff --git a/rocket/src/main/scala/ctrl_vec.scala b/rocket/src/main/scala/ctrl_vec.scala index fe76ddeb..3bc73e38 100644 --- a/rocket/src/main/scala/ctrl_vec.scala +++ b/rocket/src/main/scala/ctrl_vec.scala @@ -46,6 +46,10 @@ class ioCtrlVecInterface extends Bundle val exception = Bool(OUTPUT) val exception_ack_valid = Bool(INPUT) val exception_ack_ready = Bool(OUTPUT) + + val evac = Bool(OUTPUT) + val kill = Bool(OUTPUT) + val hold = Bool(OUTPUT) } class ioCtrlVec extends Bundle @@ -55,6 +59,7 @@ class ioCtrlVec extends Bundle val s = Bool(INPUT) val sr_ev = Bool(INPUT) val exception = Bool(INPUT) + val eret = Bool(INPUT) val replay = Bool(OUTPUT) val stalld = Bool(OUTPUT) val vfence_ready = Bool(OUTPUT) @@ -77,61 +82,64 @@ class rocketCtrlVec extends Component // | | | | | | | | vpfcntq // wen | | | | | | | | | pfq // val vcmd vimm vimm2 | fn | | | | | | | | | | fence_cv - // | | | | | | | | | | | | | | | | | waitxcpt + // | | | | | | | | | | | | | | | | | xcptwait // | | | | | | | | | | | | | | | | | | - List(N,VCMD_X, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,N,N,N,N,N,N,N,N,N),Array( - VVCFGIVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_CFGVL,N,Y,Y,N,N,Y,Y,N,N,N,N,N), - VVCFG-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, N,VEC_CFG, N,Y,Y,N,N,Y,Y,N,N,N,N,N), - VSETVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_VL, N,Y,Y,N,N,Y,Y,N,N,N,N,N), - VF-> List(Y,VCMD_I, VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,N,N,N,N,N,N,N), - VMVV-> List(Y,VCMD_TX,VIMM_X, VIMM2_X, N,VEC_FN_N, Y,Y,N,N,N,N,N,N,N,N,N,N), - VMSV-> List(Y,VCMD_TX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,N,N,N,N,N,N,N), - VFMVV-> List(Y,VCMD_TF,VIMM_X, VIMM2_X, N,VEC_FN_N, Y,Y,N,N,N,N,N,N,N,N,N,N), - FENCE_L_V-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,Y,N,N,N,N,N,N,N,N,N,N), - FENCE_G_V-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,Y,N,N,N,N,N,N,N,N,N,N), - FENCE_L_CV->List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,Y,N), - FENCE_G_CV->List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,Y,N), - VLD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), - VLW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), - VLWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), - VLH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), - VLHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), - VLB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), - VLBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), - VSD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), - VSW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), - VSH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), - VSB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), - VFLD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), - VFLW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), - VFSD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), - VFSW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), - VLSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), - VLSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), - VLSTWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), - VLSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), - VLSTHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), - VLSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), - VLSTBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), - VSSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), - VSSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), - VSSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), - VSSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), - VFLSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), - VFLSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), - VFSSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), - VFSSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), - VENQCMD-> List(Y,VCMD_A, VIMM_X, VIMM2_X, N,VEC_FN_N, N,Y,N,N,N,Y,N,N,N,Y,N,N), - VENQIMM1-> List(Y,VCMD_X, VIMM_ALU, VIMM2_X, N,VEC_FN_N, N,N,Y,N,N,N,Y,N,N,Y,N,N), - VENQIMM2-> List(Y,VCMD_X, VIMM_X, VIMM2_ALU,N,VEC_FN_N, N,N,N,Y,N,N,N,Y,N,Y,N,N), - VENQCNT-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,Y,N,N,N,Y,Y,N,N), - VWAITXCPT-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,Y) + List(N,VCMD_X, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,N,N,N,N,N,N,N,N,N,N,N,N),Array( + VVCFGIVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_CFGVL,N,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), + VVCFG-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, N,VEC_CFG, N,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), + VSETVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_VL, N,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), + VF-> List(Y,VCMD_I, VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,N,N,N,N,N,N,N,N,N,N), + VMVV-> List(Y,VCMD_TX,VIMM_X, VIMM2_X, N,VEC_FN_N, Y,Y,N,N,N,N,N,N,N,N,N,N,N,N,N), + VMSV-> List(Y,VCMD_TX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,N,N,N,N,N,N,N,N,N,N), + VFMVV-> List(Y,VCMD_TF,VIMM_X, VIMM2_X, N,VEC_FN_N, Y,Y,N,N,N,N,N,N,N,N,N,N,N,N,N), + FENCE_L_V-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,Y,N,N,N,N,N,N,N,N,N,N,N,N,N), + FENCE_G_V-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,Y,N,N,N,N,N,N,N,N,N,N,N,N,N), + FENCE_L_CV->List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,Y,N,N,N,N), + FENCE_G_CV->List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,Y,N,N,N,N), + VLD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), + VLW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), + VLWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), + VLH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), + VLHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), + VLB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), + VLBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), + VSD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), + VSW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), + VSH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), + VSB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), + VFLD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), + VFLW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), + VFSD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), + VFSW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N), + VLSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), + VLSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), + VLSTWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), + VLSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), + VLSTHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), + VLSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), + VLSTBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), + VSSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), + VSSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), + VSSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), + VSSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), + VFLSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), + VFLSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), + VFSSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), + VFSSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N), + VENQCMD-> List(Y,VCMD_A, VIMM_X, VIMM2_X, N,VEC_FN_N, N,Y,N,N,N,Y,N,N,N,Y,N,N,N,N,N), + VENQIMM1-> List(Y,VCMD_X, VIMM_ALU, VIMM2_X, N,VEC_FN_N, N,N,Y,N,N,N,Y,N,N,Y,N,N,N,N,N), + VENQIMM2-> List(Y,VCMD_X, VIMM_X, VIMM2_ALU,N,VEC_FN_N, N,N,N,Y,N,N,N,Y,N,Y,N,N,N,N,N), + VENQCNT-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,Y,N,N,N,Y,Y,N,N,N,N,N), + VXCPTEVAC-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,Y,N,N,N), + VXCPTKILL-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,N,Y,N,N), + VXCPTWAIT-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,N,N,Y,N), + VXCPTHOLD-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,N,N,N,Y) )) val wb_vec_val :: wb_sel_vcmd :: wb_sel_vimm :: wb_sel_vimm2 :: wb_vec_wen :: wb_vec_fn :: wb_vec_appvlmask :: veccs0 = veccs val wb_vec_cmdq_enq :: wb_vec_ximm1q_enq :: wb_vec_ximm2q_enq :: wb_vec_cntq_enq :: veccs1 = veccs0 val wb_vec_pfcmdq_enq :: wb_vec_pfximm1q_enq :: wb_vec_pfximm2q_enq :: wb_vec_pfcntq_enq :: veccs2 = veccs1 - val wb_vec_pfaq :: wb_vec_fence_cv :: wb_vec_waitxcpt :: Nil = veccs2 + val wb_vec_pfaq :: wb_vec_fence_cv :: wb_vec_xcptevac :: wb_vec_xcptkill :: wb_vec_xcptwait :: wb_vec_xcpthold :: Nil = veccs2 val valid_common = io.dpath.valid && io.sr_ev && wb_vec_val && !(wb_vec_appvlmask && io.dpath.appvl0) @@ -207,15 +215,24 @@ class rocketCtrlVec extends Component wb_vec_fence_cv && !io.iface.vfence_ready ) - val reg_waitxcpt = Reg(resetVal = Bool(false)) - val do_waitxcpt = valid_common && wb_vec_waitxcpt && !io.replay + val reg_xcptwait = Reg(resetVal = Bool(false)) + val do_xcptwait = valid_common && wb_vec_xcptwait && !io.replay - when (do_waitxcpt) { reg_waitxcpt := Bool(true) } - when (io.iface.exception_ack_valid) { reg_waitxcpt := Bool(false) } + when (do_xcptwait) { reg_xcptwait := Bool(true) } + when (io.iface.exception_ack_valid) { reg_xcptwait := Bool(false) } io.iface.exception := io.exception && io.sr_ev - io.iface.exception_ack_ready := reg_waitxcpt + io.iface.exception_ack_ready := reg_xcptwait - io.stalld := reg_waitxcpt + val reg_hold = Reg(resetVal = Bool(false)) + + when (wb_vec_xcpthold) { reg_hold := Bool(true) } + when (io.eret) { reg_hold := Bool(false) } + + io.iface.evac := wb_vec_xcptevac.toBool + io.iface.kill := wb_vec_xcptkill.toBool + io.iface.hold := reg_hold + + io.stalld := reg_xcptwait io.vfence_ready := !io.sr_ev || io.iface.vfence_ready } diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index bcdea1e6..fa69077b 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -383,10 +383,6 @@ class rocketDpath extends Component vec.io.vecbankcnt := pcr.io.vecbankcnt vec.io.wdata := wb_reg_vec_wdata vec.io.rs2 := wb_reg_rs2 - vec.io.vechold := pcr.io.vechold - vec.io.pcrw.addr := wb_reg_raddr2 - vec.io.pcrw.en := io.ctrl.wen_pcr - vec.io.pcrw.data := wb_reg_wdata pcr.io.vec_appvl := vec.io.appvl pcr.io.vec_nxregs := vec.io.nxregs diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index b5986bfe..a3564b69 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -79,7 +79,6 @@ class ioDpathPCR extends Bundle() val irq_ipi = Bool(OUTPUT); val vecbank = Bits(8, OUTPUT) val vecbankcnt = UFix(4, OUTPUT) - val vechold = Bool(OUTPUT) val vec_appvl = UFix(12, INPUT) val vec_nxregs = UFix(6, INPUT) val vec_nfregs = UFix(6, INPUT) @@ -101,7 +100,6 @@ class rocketDpathPCR extends Component val reg_k1 = Reg() { Bits() }; val reg_ptbr = Reg() { UFix() }; val reg_vecbank = Reg(resetVal = Bits("b1111_1111", 8)) - val reg_vechold = Reg() { Bool() } val reg_error_mode = Reg(resetVal = Bool(false)); val reg_status_vm = Reg(resetVal = Bool(false)); @@ -143,8 +141,6 @@ class rocketDpathPCR extends Component cnt = cnt + reg_vecbank(i) io.vecbankcnt := cnt(3,0) - io.vechold := reg_vechold - val badvaddr_sign = Mux(io.w.data(VADDR_BITS-1), ~io.w.data(63,VADDR_BITS) === UFix(0), io.w.data(63,VADDR_BITS) != UFix(0)) when (io.badvaddr_wen) { reg_badvaddr := Cat(badvaddr_sign, io.w.data(VADDR_BITS-1,0)).toUFix; @@ -174,7 +170,6 @@ class rocketDpathPCR extends Component when (io.eret) { reg_status_s := reg_status_ps; reg_status_et := Bool(true); - reg_vechold := Bool(false) } when (reg_count === reg_compare) { @@ -212,7 +207,6 @@ class rocketDpathPCR extends Component when (waddr === PCR_K1) { reg_k1 := wdata; } when (waddr === PCR_PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; } when (waddr === PCR_VECBANK) { reg_vecbank := wdata(7,0) } - when (waddr === PCR_VEC_HOLD) { reg_vechold := reg_status_ev && wdata(0) } } rdata := Bits(0, 64) diff --git a/rocket/src/main/scala/dpath_vec.scala b/rocket/src/main/scala/dpath_vec.scala index 95653b98..f8270002 100644 --- a/rocket/src/main/scala/dpath_vec.scala +++ b/rocket/src/main/scala/dpath_vec.scala @@ -12,10 +12,7 @@ class ioDpathVecInterface extends Bundle val vximm1q_bits = Bits(SZ_VIMM, OUTPUT) val vximm2q_bits = Bits(SZ_VSTRIDE, OUTPUT) val vcntq_bits = Bits(SZ_VLEN, OUTPUT) - val backup = Bool(OUTPUT) - val backup_addr = Bits(64, OUTPUT) - val kill = Bool(OUTPUT) - val hold = Bool(OUTPUT) + val evac_addr = Bits(64, OUTPUT) } class ioDpathVec extends Bundle @@ -30,8 +27,6 @@ class ioDpathVec extends Bundle val vecbankcnt = UFix(4, INPUT) val wdata = Bits(64, INPUT) val rs2 = Bits(64, INPUT) - val vechold = Bool(INPUT) - val pcrw = new ioWritePort() val wen = Bool(OUTPUT) val appvl = UFix(12, OUTPUT) val nxregs = UFix(6, OUTPUT) @@ -162,10 +157,7 @@ class rocketDpathVec extends Component io.iface.vcntq_bits := io.wdata(SZ_VLEN-1, 0) - io.iface.backup := io.pcrw.en && (io.pcrw.addr === PCR_VEC_BACKUP) - io.iface.backup_addr := io.pcrw.data - io.iface.kill := io.pcrw.en && (io.pcrw.addr === PCR_VEC_KILL) - io.iface.hold := io.vechold + io.iface.evac_addr := io.wdata io.ctrl.valid := io.valid io.ctrl.inst := io.inst diff --git a/rocket/src/main/scala/instructions.scala b/rocket/src/main/scala/instructions.scala index a6e3c839..bf985739 100644 --- a/rocket/src/main/scala/instructions.scala +++ b/rocket/src/main/scala/instructions.scala @@ -33,11 +33,11 @@ object Instructions val SLL = Bits("b?????_?????_?????_0000000001_0110011",32); val SLT = Bits("b?????_?????_?????_0000000010_0110011",32); val SLTU = Bits("b?????_?????_?????_0000000011_0110011",32); - val riscvXOR = Bits("b?????_?????_?????_0000000100_0110011",32); + val riscvXOR = Bits("b?????_?????_?????_0000000100_0110011",32); val SRL = Bits("b?????_?????_?????_0000000101_0110011",32); val SRA = Bits("b?????_?????_?????_1000000101_0110011",32); - val riscvOR = Bits("b?????_?????_?????_0000000110_0110011",32); - val riscvAND = Bits("b?????_?????_?????_0000000111_0110011",32); + val riscvOR = Bits("b?????_?????_?????_0000000110_0110011",32); + val riscvAND = Bits("b?????_?????_?????_0000000111_0110011",32); val MUL = Bits("b?????_?????_?????_0000001000_0110011",32); val MULH = Bits("b?????_?????_?????_0000001001_0110011",32); val MULHSU = Bits("b?????_?????_?????_0000001010_0110011",32); @@ -253,7 +253,10 @@ object Instructions val VENQIMM1 = Bits("b00000_?????_?????_1000000001_1111011",32) val VENQIMM2 = Bits("b00000_?????_?????_1000000010_1111011",32) val VENQCNT = Bits("b00000_?????_?????_1000000011_1111011",32) - val VWAITXCPT = Bits("b00000_00000_00000_1100000000_1111011",32) + val VXCPTEVAC = Bits("b00000_?????_00000_1100000000_1111011",32) + val VXCPTKILL = Bits("b00000_00000_00000_1100000001_1111011",32) + val VXCPTWAIT = Bits("b00000_00000_00000_1100000010_1111011",32) + val VXCPTHOLD = Bits("b00000_00000_00000_1100000011_1111011",32) val NOP = ADDI & Bits("b00000000000000000000001111111111", 32); }