riscv/rocket-chip
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refactored vector exception handling interface

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This commit is contained in:
Yunsup Lee
2012-03-13 23:45:10 -07:00
parent b100544b25
commit 040d62f372
8 changed files with 91 additions and 90 deletions
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7
rocket/src/main/scala/consts.scala
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@ -7,7 +7,7 @@ object Constants
{
val HAVE_RVC = false
val HAVE_FPU = true
val HAVE_VEC = true
val HAVE_VEC = false
val BR_N = UFix(0, 4);
val BR_EQ = UFix(1, 4);
@ -144,11 +144,6 @@ object Constants
val PCR_VECBANK = UFix(18, 5);
val PCR_VECCFG = UFix(19, 5);
// temporaries for vector, these will go away
val PCR_VEC_BACKUP = UFix(29, 5)
val PCR_VEC_KILL = UFix(30, 5)
val PCR_VEC_HOLD = UFix(31, 5)
// definition of bits in PCR status reg
val SR_ET = 0; // enable traps
val SR_EF = 1; // enable floating point