parameterize the scoreboards
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6c2d8a37ae
commit
0366465cb1
@ -517,40 +517,44 @@ class rocketCtrl extends Component
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wb_reg_fp_val := mem_reg_fp_val
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wb_reg_fp_val := mem_reg_fp_val
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}
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}
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val sboard = new rocketCtrlSboard();
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val sboard = new rocketCtrlSboard(32, 3, 2);
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sboard.io.raddra := id_raddr2.toUFix;
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sboard.io.r(0).addr := id_raddr2.toUFix;
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sboard.io.raddrb := id_raddr1.toUFix;
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sboard.io.r(1).addr := id_raddr1.toUFix;
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sboard.io.raddrc := id_waddr.toUFix;
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sboard.io.r(2).addr := id_waddr.toUFix;
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// scoreboard set (for D$ misses, div, mul)
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// scoreboard set (for D$ misses, div, mul)
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sboard.io.set := wb_reg_div_mul_val || wb_reg_dcache_miss && wb_reg_wen;
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sboard.io.w(0).en := wb_reg_div_mul_val || wb_reg_dcache_miss && wb_reg_wen
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sboard.io.seta := io.dpath.wb_waddr;
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sboard.io.w(0).data := Bool(true)
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sboard.io.w(0).addr := io.dpath.wb_waddr
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sboard.io.clr := io.dpath.sboard_clr;
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sboard.io.w(1).en := io.dpath.sboard_clr
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sboard.io.clra := io.dpath.sboard_clra;
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sboard.io.w(1).data := Bool(false)
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sboard.io.w(1).addr := io.dpath.sboard_clra
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val id_stall_raddr2 = id_renx2.toBool && sboard.io.stalla;
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val id_stall_raddr2 = id_renx2.toBool && sboard.io.r(0).data
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val id_stall_raddr1 = id_renx1.toBool && sboard.io.stallb;
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val id_stall_raddr1 = id_renx1.toBool && sboard.io.r(1).data
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val id_stall_waddr = id_wen.toBool && sboard.io.stallc;
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val id_stall_waddr = id_wen.toBool && sboard.io.r(2).data
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var id_stall_fpu = Bool(false)
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var id_stall_fpu = Bool(false)
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if (HAVE_FPU) {
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if (HAVE_FPU) {
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val fp_sboard = new rocketCtrlSboard();
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val fp_sboard = new rocketCtrlSboard(32, 4, 2);
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fp_sboard.io.raddra := id_raddr1.toUFix;
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fp_sboard.io.r(0).addr := id_raddr1.toUFix
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fp_sboard.io.raddrb := id_raddr2.toUFix;
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fp_sboard.io.r(1).addr := id_raddr2.toUFix
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fp_sboard.io.raddrc := id_raddr3.toUFix;
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fp_sboard.io.r(2).addr := id_raddr3.toUFix
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fp_sboard.io.raddrd := id_waddr.toUFix;
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fp_sboard.io.r(3).addr := id_waddr.toUFix
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fp_sboard.io.set := wb_reg_dcache_miss && wb_reg_fp_wen;
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fp_sboard.io.w(0).en := wb_reg_dcache_miss && wb_reg_fp_wen
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fp_sboard.io.seta := io.dpath.wb_waddr;
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fp_sboard.io.w(0).data := Bool(true)
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fp_sboard.io.w(0).addr := io.dpath.wb_waddr
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fp_sboard.io.clr := io.dpath.fp_sboard_clr;
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fp_sboard.io.w(1).en := io.dpath.fp_sboard_clr
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fp_sboard.io.clra := io.dpath.fp_sboard_clra;
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fp_sboard.io.w(1).data := Bool(false)
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fp_sboard.io.w(1).addr := io.dpath.fp_sboard_clra
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id_stall_fpu = io.fpu.dec.ren1 && fp_sboard.io.stalla ||
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id_stall_fpu = io.fpu.dec.ren1 && fp_sboard.io.r(0).data ||
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io.fpu.dec.ren2 && fp_sboard.io.stallb ||
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io.fpu.dec.ren2 && fp_sboard.io.r(1).data ||
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io.fpu.dec.ren3 && fp_sboard.io.stallc ||
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io.fpu.dec.ren3 && fp_sboard.io.r(2).data ||
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io.fpu.dec.wen && fp_sboard.io.stalld
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io.fpu.dec.wen && fp_sboard.io.r(3).data
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}
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}
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// exception handling
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// exception handling
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@ -2,35 +2,31 @@ package Top
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import Chisel._
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import Chisel._
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import Node._;
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import Node._;
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import Constants._;
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class ioCtrlSboard extends Bundle()
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class rocketCtrlSboard(entries: Int, nread: Int, nwrite: Int) extends Component
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{
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{
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val clr = Bool(INPUT);
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class read_port extends Bundle {
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val clra = UFix(5, INPUT);
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val addr = UFix(log2up(entries), INPUT)
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val set = Bool(INPUT);
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val data = Bool(OUTPUT)
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val seta = UFix(5, INPUT);
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}
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val raddra = UFix(5, INPUT);
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class write_port extends Bundle {
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val raddrb = UFix(5, INPUT);
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val en = Bool(INPUT)
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val raddrc = UFix(5, INPUT);
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val addr = UFix(log2up(entries), INPUT)
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val raddrd = UFix(5, INPUT);
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val data = Bool(INPUT)
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val stalla = Bool(OUTPUT);
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val stallb = Bool(OUTPUT);
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val stallc = Bool(OUTPUT);
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val stalld = Bool(OUTPUT);
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}
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}
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class rocketCtrlSboard extends Component
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val io = new Bundle {
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{
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val r = Vec(nread) { new read_port() }
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override val io = new ioCtrlSboard();
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val w = Vec(nwrite) { new write_port() }
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val reg_busy = Reg(resetVal = Bits(0, 32));
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}
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val set_mask = io.set.toUFix << io.seta;
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val busybits = Reg(resetVal = Bits(0, entries));
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val clr_mask = ~(io.clr.toUFix << io.clra);
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reg_busy := (reg_busy | set_mask) & clr_mask
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for (i <- 0 until nread)
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io.r(i).data := busybits(io.r(i).addr)
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io.stalla := reg_busy(io.raddra).toBool;
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io.stallb := reg_busy(io.raddrb).toBool;
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var wdata = busybits
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io.stallc := reg_busy(io.raddrc).toBool;
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for (i <- 0 until nwrite)
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io.stalld := reg_busy(io.raddrd).toBool;
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wdata = wdata.bitSet(io.w(i).addr, Mux(io.w(i).en, io.w(i).data, wdata(io.w(i).addr)))
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busybits := wdata
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}
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}
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