From 0366465cb100910fea87ed545ccc716135860395 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@eecs.berkeley.edu>
Date: Mon, 13 Feb 2012 18:12:23 -0800
Subject: [PATCH] parameterize the scoreboards

---
 rocket/src/main/scala/ctrl.scala      | 52 ++++++++++++++-------------
 rocket/src/main/scala/ctrl_util.scala | 52 +++++++++++++--------------
 2 files changed, 52 insertions(+), 52 deletions(-)

diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala
index 49ca4dbc..2897b41e 100644
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@@ -517,40 +517,44 @@ class rocketCtrl extends Component
     wb_reg_fp_val      := mem_reg_fp_val
   }
 
-  val sboard = new rocketCtrlSboard(); 
-  sboard.io.raddra  := id_raddr2.toUFix;
-  sboard.io.raddrb  := id_raddr1.toUFix;
-  sboard.io.raddrc  := id_waddr.toUFix;
+  val sboard = new rocketCtrlSboard(32, 3, 2);
+  sboard.io.r(0).addr := id_raddr2.toUFix;
+  sboard.io.r(1).addr := id_raddr1.toUFix;
+  sboard.io.r(2).addr := id_waddr.toUFix;
 
   // scoreboard set (for D$ misses, div, mul)
-  sboard.io.set     := wb_reg_div_mul_val || wb_reg_dcache_miss && wb_reg_wen;
-  sboard.io.seta    := io.dpath.wb_waddr;
+  sboard.io.w(0).en := wb_reg_div_mul_val || wb_reg_dcache_miss && wb_reg_wen
+  sboard.io.w(0).data := Bool(true)
+  sboard.io.w(0).addr := io.dpath.wb_waddr
 
-  sboard.io.clr    := io.dpath.sboard_clr;
-  sboard.io.clra   := io.dpath.sboard_clra;
+  sboard.io.w(1).en := io.dpath.sboard_clr
+  sboard.io.w(1).data := Bool(false)
+  sboard.io.w(1).addr := io.dpath.sboard_clra
 
-  val id_stall_raddr2 = id_renx2.toBool && sboard.io.stalla;
-  val id_stall_raddr1 = id_renx1.toBool && sboard.io.stallb;
-  val id_stall_waddr  = id_wen.toBool && sboard.io.stallc;
+  val id_stall_raddr2 = id_renx2.toBool && sboard.io.r(0).data
+  val id_stall_raddr1 = id_renx1.toBool && sboard.io.r(1).data
+  val id_stall_waddr  = id_wen.toBool && sboard.io.r(2).data
 
   var id_stall_fpu = Bool(false)
   if (HAVE_FPU) {
-    val fp_sboard = new rocketCtrlSboard(); 
-    fp_sboard.io.raddra  := id_raddr1.toUFix;
-    fp_sboard.io.raddrb  := id_raddr2.toUFix;
-    fp_sboard.io.raddrc  := id_raddr3.toUFix;
-    fp_sboard.io.raddrd  := id_waddr.toUFix;
+    val fp_sboard = new rocketCtrlSboard(32, 4, 2);
+    fp_sboard.io.r(0).addr := id_raddr1.toUFix
+    fp_sboard.io.r(1).addr := id_raddr2.toUFix
+    fp_sboard.io.r(2).addr := id_raddr3.toUFix
+    fp_sboard.io.r(3).addr := id_waddr.toUFix
 
-    fp_sboard.io.set     := wb_reg_dcache_miss && wb_reg_fp_wen;
-    fp_sboard.io.seta    := io.dpath.wb_waddr;
+    fp_sboard.io.w(0).en := wb_reg_dcache_miss && wb_reg_fp_wen
+    fp_sboard.io.w(0).data := Bool(true)
+    fp_sboard.io.w(0).addr := io.dpath.wb_waddr
 
-    fp_sboard.io.clr    := io.dpath.fp_sboard_clr;
-    fp_sboard.io.clra   := io.dpath.fp_sboard_clra;
+    fp_sboard.io.w(1).en := io.dpath.fp_sboard_clr
+    fp_sboard.io.w(1).data := Bool(false)
+    fp_sboard.io.w(1).addr := io.dpath.fp_sboard_clra
 
-    id_stall_fpu = io.fpu.dec.ren1 && fp_sboard.io.stalla ||
-                   io.fpu.dec.ren2 && fp_sboard.io.stallb ||
-                   io.fpu.dec.ren3 && fp_sboard.io.stallc ||
-                   io.fpu.dec.wen  && fp_sboard.io.stalld
+    id_stall_fpu = io.fpu.dec.ren1 && fp_sboard.io.r(0).data ||
+                   io.fpu.dec.ren2 && fp_sboard.io.r(1).data ||
+                   io.fpu.dec.ren3 && fp_sboard.io.r(2).data ||
+                   io.fpu.dec.wen  && fp_sboard.io.r(3).data
   } 
 
   // exception handling
diff --git a/rocket/src/main/scala/ctrl_util.scala b/rocket/src/main/scala/ctrl_util.scala
index 8d99b83c..86ffcd78 100644
--- a/rocket/src/main/scala/ctrl_util.scala
+++ b/rocket/src/main/scala/ctrl_util.scala
@@ -2,35 +2,31 @@ package Top
 
 import Chisel._
 import Node._;
-import Constants._;
 
-class ioCtrlSboard extends Bundle()
+class rocketCtrlSboard(entries: Int, nread: Int, nwrite: Int) extends Component
 {
-  val clr    = Bool(INPUT);
-  val clra   = UFix(5, INPUT);
-  val set     = Bool(INPUT);
-  val seta    = UFix(5, INPUT);
-  val raddra  = UFix(5, INPUT);
-  val raddrb  = UFix(5, INPUT);
-  val raddrc  = UFix(5, INPUT);
-  val raddrd  = UFix(5, INPUT);
-  val stalla  = Bool(OUTPUT);
-  val stallb  = Bool(OUTPUT);
-  val stallc  = Bool(OUTPUT);
-  val stalld  = Bool(OUTPUT);
-}
+  class read_port extends Bundle {
+    val addr = UFix(log2up(entries), INPUT)
+    val data = Bool(OUTPUT)
+  }
+  class write_port extends Bundle {
+    val en = Bool(INPUT)
+    val addr = UFix(log2up(entries), INPUT)
+    val data = Bool(INPUT)
+  }
 
-class rocketCtrlSboard extends Component
-{
-  override val io = new ioCtrlSboard();
-  val reg_busy = Reg(resetVal = Bits(0, 32));
-  
-  val set_mask =   io.set.toUFix << io.seta;
-  val clr_mask = ~(io.clr.toUFix << io.clra);
-  reg_busy := (reg_busy | set_mask) & clr_mask
-  
-  io.stalla  := reg_busy(io.raddra).toBool;
-  io.stallb  := reg_busy(io.raddrb).toBool;
-  io.stallc  := reg_busy(io.raddrc).toBool;
-  io.stalld  := reg_busy(io.raddrd).toBool;
+  val io = new Bundle {
+    val r = Vec(nread) { new read_port() }
+    val w = Vec(nwrite) { new write_port() }
+  }
+
+  val busybits = Reg(resetVal = Bits(0, entries));
+
+  for (i <- 0 until nread)
+    io.r(i).data := busybits(io.r(i).addr)
+
+  var wdata = busybits
+  for (i <- 0 until nwrite)
+    wdata = wdata.bitSet(io.w(i).addr, Mux(io.w(i).en, io.w(i).data, wdata(io.w(i).addr)))
+  busybits := wdata
 }